®
AS7C1026B
3/26/04, v 1.3 Alliance Semiconductor P. 7 of 10
AC test conditions
Notes
1 During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 These parameters are specified with C
L
= 5 pF, as in Figures B. Transition is measured ± 500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6WE
is high for read cycle.
7CE
and OE are low for read cycle.
8 Address is valid prior to or coincident with CE
transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
168
Ω
Thevenin Equivalent:
D
OUT
+1.728 V
255
Ω
C
13
480
Ω
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.5V
Figure A: Input pulse
2 ns
D
OUT
– Output load: see Figure B.
– Input pulse level: GND to 3.5 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5
