REV. C
AD624
–6–
Figure 19. Large Signal Pulse
Response and Settling Time, G = 1
Figure 22. Range Signal Pulse
Response and Settling Time,
G = 500
20
8 TO 8
12 TO 12
0
OUTPUT
STEP V
4 TO 4
4 TO 4
8 TO 8
12 TO 12
15105
SETTLING TIME s
1%
1%
0.1%
0.01%
0.1%
0.01%
Figure 20. Settling Time Gain = 100
20
8 TO 8
12 TO 12
0
OUTPUT
STEP V
4 TO 4
4 TO 4
8 TO 8
12 TO 12
15105
SETTLING TIME s
0.1%
0.1%
1%
1%
0.01%
0.01%
Figure 23. Settling Time Gain = 1000
Figure 21. Large Signal Pulse
Response and Settling Time,
G = 100
Figure 24. Large Signal Pulse
Response and Settling Time,
G = 1000
REV. C
AD624
–7–
AD624
+V
S
V
OUT
10k
1%
1k
10T
10k
1%
RG
1
G = 100
G = 200
G = 500
RG
2
V
S
200
0.1%
100k
1%
500
0.1%
1k
0.1%
INPUT
20V p-p
Figure 25. Settling Time Test Circuit
THEORY OF OPERATION
The AD624 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp instrumentation
amplifier. Monolithic construction and laser-wafer-trimming
allow the tight matching and tracking of circuit components and
the high level of performance that this circuit architecture is ca-
pable of.
A preamp section (Q1Q4) develops the programmed gain by
the use of feedback concepts. Feedback from the outputs of A1
and A2 forces the collector currents of Q1Q4 to be constant
thereby impressing the input voltage across R
G
.
The gain is set by choosing the value of R
G
from the equation,
Gain =
40 k
R
G
+ 1. The value of R
G
also sets the transconduct-
ance of the input preamp stage increasing it asymptotically to
the transconductance of the input transistors as R
G
is reduced
for larger gains. This has three important advantages. First, this
approach allows the circuit to achieve a very high open loop gain
of 3 × 10
8
at a programmed gain of 1000 thus reducing gain
related errors to a negligible 3 ppm. Second, the gain bandwidth
product which is determined by C3 or C4 and the input trans-
conductance, reaches 25 MHz. Third, the input voltage noise
reduces to a value determined by the collector current of the
input transistors for an RTI noise of 4 nV/Hz at G 500.
AD624
+V
S
100
200
RG
2
V
S
16.2k
+V
S
1/2
AD712
9.09k
G1, 100, 200
1k
1F
G500
100
1F
1.62M
V
S
1F
16.2k
1.82k
500
1/2
AD712
Figure 26. Noise Test Circuit
INPUT CONSIDERATIONS
Under input overload conditions the user will see R
G
+ 100
and two diode drops (~1.2 V) between the plus and minus
inputs, in either direction. If safe overload current under all
conditions is assumed to be 10 mA, the maximum overload
voltage is ~ ±2.5 V. While the AD624 can withstand this con-
tinuously, momentary overloads of ±10 V will not harm the
device. On the other hand the inputs should never exceed the
supply voltage.
The AD524 should be considered in applications that require
protection from severe input overload. If this is not possible,
external protection resistors can be put in series with the inputs
of the AD624 to augment the internal (50 ) protection resis-
tors. This will most seriously degrade the noise performance.
For this reason the value of these resistors should be chosen to
be as low as possible and still provide 10 mA of current limiting
under maximum continuous overload conditions. In selecting
the value of these resistors, the internal gain setting resistor and
the 1.2 volt drop need to be considered. For example, to pro-
tect the device from a continuous differential overload of 20 V
at a gain of 100, 1.9 k of resistance is required. The internal
gain resistor is 404 ; the internal protect resistor is 100 .
There is a 1.2 V drop across D1 or D2 and the base-emitter
junction of either Q1 and Q3 or Q2 and Q4 as shown in Figure
27, 1400 of external resistance would be required (700 in
series with each input). The RTI noise in this case would be
4 KTR
ext
+(4 nV / Hz )
2
= 6.2 nV / Hz
50
13
50A
I1
50A
C3
I2
50A
R57
20k
R56
20k
500
SENSE
+IN
V
O
REF
I4
50A
200
100
4445
80.2
124
225.3
IN
V
S
RG
1
RG
2
C4
VB
A2
R52
10k
R55
10k
A3
R53
10k
R54
10k
+V
S
50
Q1, Q3
Q2,
Q4
A1
Figure 27. Simplified Circuit of Amplifier; Gain Is Defined
as (R56 + R57)/(R
G
) + 1. For a Gain of 1, R
G
Is an Open
Circuit.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may
be adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many small-
signal high-gain applications that dont have this capability.
Voltage offset and offset drift each have two components; input
and output. Input offset is that component of offset that is
REV. C
AD624
–8–
directly proportional to gain i.e., input offset as measured at
the output at G = 100 is 100 times greater than at G = 1.
Output offset is independent of gain. At low gains, output offset
drift is dominant, while at high gains input offset drift domi-
nates. Therefore, the output offset voltage drift is normally
specified as drift at G = 1 (where input effects are insignificant),
while input offset voltage drift is given by drift specification at a
high gain (where output offset effects are negligible). All input-
related numbers are referred to the input (RTI) which is to say
that the effect on the output is G times larger. Voltage offset
vs. power supply is also specified at one or more gain settings
and is also RTI.
By separating these errors, one can evaluate the total error inde-
pendent of the gain setting used. In a given gain configura-
tion both errors can be combined to give a total error referred to
the input (R.T.I.) or output (R.T.O.) by the following formula:
Total Error R.T.I. = input error + (output error/gain)
Total Error R.T.O. = (Gain × input error) + output error
As an illustration, a typical AD624 might have a +250 µV out-
put offset and a 50 µV input offset. In a unity gain configura-
tion, the total output offset would be 200 µV or the sum of the
two. At a gain of 100, the output offset would be 4.75 mV
or: +250 µV + 100 (50 µV) = 4.75 mV.
The AD624 provides for both input and output offset adjust-
ment. This optimizes nulling in very high precision applications
and minimizes offset voltage effects in switched gain applica-
tions. In such applications the input offset is adjusted first at the
highest programmed gain, then the output offset is adjusted at
G = 1.
GAIN
The AD624 includes high accuracy pretrimmed internal
gain resistors. These allow for single connection program-
ming of gains of 1, 100, 200 and 500. Additionally, a variety
of gains including a pretrimmed gain of 1000 can be achieved
through series and parallel combinations of the internal resis-
tors. Table I shows the available gains and the appropriate
pin connections and gain temperature coefficients.
The gain values achieved via the combination of internal
resistors are extremely useful. The temperature coefficient of the
gain is dependent primarily on the mismatch of the temperature
coefficients of the various internal resistors. Tracking of these
resistors is extremely tight resulting in the low gain TCs shown
in Table I.
If the desired value of gain is not attainable using the inter-
nal resistors, a single external resistor can be used to achieve
any gain between 1 and 10,000. This resistor connected between
AD624
G = 100
RG
2
V
S
OUTPUT
SIGNAL
COMMON
V
OUT
10k
INPUT
RG
1
G = 200
G = 500
+INPUT
INPUT
OFFSET
NULL
+V
S
Figure 28. Operating Connections for G = 200
Table I.
Temperature
Gain Coefficient Pin 3
(Nominal) (Nominal) to Pin Connect Pins
1 0 ppm/°C ––
100 1.5 ppm/°C13
125 5 ppm/°C 13 11 to 16
137 5.5 ppm/°C 13 11 to 12
186.5 6.5 ppm/°C 13 11 to 12 to 16
200 3.5 ppm/°C12
250 5.5 ppm/°C 12 11 to 13
333 15 ppm/°C 12 11 to 16
375 0.5 ppm/°C 12 13 to 16
500 10 ppm/°C11
624 5 ppm/°C 11 13 to 16
688 1.5 ppm/°C 11 11 to 12; 13 to 16
831 +4 ppm/°C 11 16 to 12
1000 0 ppm/°C 11 16 to 12; 13 to 11
Pins 3 and 16 programs the gain according to the formula
R
G
=
40k
G 1
(see Figure 29). For best results R
G
should be a precision resis-
tor with a low temperature coefficient. An external R
G
affects both
gain accuracy and gain drift due to the mismatch between it and
the internal thin-film resistors R56 and R57. Gain accuracy is
determined by the tolerance of the external R
G
and the absolute
accuracy of the internal resistors (±20%). Gain drift is determined
by the mismatch of the temperature coefficient of R
G
and the tem-
perature coefficient of the internal resistors (15 ppm/°C typ),
and the temperature coefficient of the internal interconnections.
AD624
RG
2
V
S
REFERENCE
V
OUT
INPUT
RG
1
2.105k
+INPUT
+V
S
OR
1.5k
1k
G = + 1 = 20 20%
40.000
2.105
Figure 29. Operating Connections for G = 20
The AD624 may also be configured to provide gain in the out-
put stage. Figure 30 shows an H pad attenuator connected to
the reference and sense lines of the AD624. The values of R1,
R2 and R3 should be selected to be as low as possible to mini-
mize the gain variation and reduction of CMRR. Varying R2
will precisely set the gain without affecting CMRR. CMRR is
determined by the match of R1 and R3.
AD624
G = 100
RG
2
V
S
V
OUT
INPUT
RG
1
G = 200
G = 500
+INPUT
+V
S
R
L
R3
6k
R2
5k
R1
6k
(R
2
||20k) + R
1
+ R
3
)
(R
2
||20k)
G =
(R
1
+ R
2
+ R
3
) || R
L
2k
Figure 30. Gain of 2500

AD624SD/883B

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Instrumentation Amplifiers LOW NOISE HI PREC
Lifecycle:
New from this manufacturer.
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