LTM4622
13
Rev F
For more information www.analog.com
APPLICATIONS INFORMATION
tracked up and down with another regulator. Figure4 and
Figure5 show an example waveform and schematic of a
Ratiometric tracking where the slave regulators output
slew rate is proportional to the master’s.
Since the slave regulators TRACK/SS is connected to
the masters output through a R
TR(TOP)
/R
TR(BOT)
resistor
The R
FB(SL)
is the feedback resistor and the R
TR(TOP)
/
R
TR(BOT)
is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure5.
Following the upper equation, the masters output slew
rate (MR) and the slaves output slew rate (SR) in Volts/
Time is determined by:
MR
SR
=
R
FB(SL)
R
FB(SL)
+ 60.4k
R
TR(BOT)
R
TR(TOP)
+ R
TR(BOT)
For example, V
OUT(MA)
= 1.5V, MR = 1.4V/1ms and
V
OUT(SL)
= 1.2V, SR = 1.2V/1ms. From the equation, we
could solve out that R
TR(TOP)
=60.4k and R
TR(BOT)
= 40.2k
is a good combination for the Ratiometric tracking.
The TRACK pins will have the 1.5µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
The Coincident output tracking can be recognized as a
special Ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slaves output
slew rate (SR), as waveform shown in Figure6.
Figure5. Example Schematic of Ratiometric
Output Voltage Tracking
Figure6. Output Coincident Tracking Waveform
TIME
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT VOLTAGE
4622 F06
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should sat
-
isfy the following equation during the start-up.
V
OUT(SL)
R
FB(SL)
R
FB(SL)
+ 60.4k
=
V
OUT(MA)
R
TR(BOT)
R
TR(TOP)
+ R
TR(BOT)
Figure4. Output Ratiometric Tracking Waveform
TIME
SLAVE OUTPUT
MASTER OUTPUT
OUTPUT VOLTAGE
4622 F04
40.2k
4622 F05
10µF
25V
V
IN
4V TO 20V
V
OUT1
1.5V, 2.5A
47µF
4V
0.1µF
V
OUT1
V
OUT2
1.2V, 2.5A
47µF
4V
V
OUT2
FB1
COMP1
COMP2
FREQ
GND
LTM4622
PGOOD1 PGOOD2
V
IN
RUN1
RUN2
INTV
CC
SYNC/MODE
TRACK/SS1
TRACK/SS2
60.4k
40.2k
60.4k
FB2
V
OUT1
LTM4622
14
Rev F
For more information www.analog.com
APPLICATIONS INFORMATION
From the equation, we could easily find out that, in the
Coincident tracking, the slave regulators TRACK/SS pin
resistor divider is always the same as its feedback divider.
R
FB(SL)
R
FB(SL)
+ 60.4k
=
R
TR(BOT)
R
TR(TOP)
+ R
TR(BOT)
For example, R
TR(TOP)
= 60.4k and R
TR(BOT)
= 60.4k is a
good combination for Coincident tracking for V
OUT(MA)
=
1.5V and V
OUT(SL)
= 1.2V application.
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a ±8% window around the regulation point. A resistor can
be pulled up to a particular supply voltage for monitoring.
To prevent unwanted PGOOD glitches during transients
or dynamic V
OUT
changes, the LTM4622’s PGOOD falling
edge includes a blanking delay of approximately 40µs.
Stability compensation
The LTM4622 module internal compensation loop is
designed and optimized for low ESR ceramic output
capacitors only application. Table7 is provided for most
application requirements. The LTpowerCAD Design Tool
is available to down for control loop optimization.
RUN Enable
Pulling the RUN pin to ground forces the LTM4622 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Trying the RUN pin
voltage above 1.27V will turn on the entire chip.
Low Input Application
The LTM4622 is capable to run from 3.3V input when
the V
IN
pin is tied to INTV
CC
pin. See Figure27 for the
application circuit. Please note the INTV
CC
pin has 3.6V
ABS MAX voltage rating.
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTM4622 can safely power up into
a pre-biased output without discharging it.
The LTM4622 accomplishes this by forcing discontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.6V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
Overtemperature Protection
The internal overtemperature protection monitors the
junction temperature of the module. If the junction
temperature reaches approximately 160°C, both power
switches will be turned off until the temperature drops
about 15°C cooler.
Input Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTM4622 constantly
monitors each V
IN
pin for an overvoltage condition. When
V
IN
rises above 22.5V, the regulator suspends operation
by shutting off both power MOSFETs on the correspond-
ing channel. Once V
IN
drops below 21.5V, the regulator
immediately resumes normal operation. The regulator
executes its soft-start function when exiting an overvolt-
age condition.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools
that leverage the outcome of thermal modeling, simula-
tion, and correlation to hardware evaluation performed
on a µModule package mounted to a hardware test
LTM4622
15
Rev F
For more information www.analog.com
APPLICATIONS INFORMATION
board—also defined by JESD51-9 (Test Boards for Area
Array Surface Mount Package Thermal Measurements).
The motivation for providing these thermal coefficients in
found in JESD51-12 (Guidelines for Reporting and Using
Electronic Package Thermal Information).
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulators thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet can
be used in a manner that yields insight and guidance per-
taining to ones application usage, and can be adapted to
correlate thermal per
formance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coef-
ficients are quoted or paraphrased below:
1.
θ
JA
, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air ther-
mal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred
to as still air although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD 51-9 defined test board, which
does not reflect an actual application or viable operat-
ing condition.
2. θ
JCbottom
, the thermal resistance from junction to
ambient, is the natural convection junction-to-ambi-
ent air thermal resistance measured in a one cubic
foot sealed enclosure. This environment is sometimes
referred to as still air although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD 51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
3. θ
JCtop
, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
JCbottom
, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θ
JB
, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θ
JCbottom
and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD 51-9.
Figure7. Graphical Representation of JESD 51-12 Thermal Coefficients
4622 F07
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION
AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE

LTM4622IY#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Ultrathin Dual 20VIN, 3A Step-Down Module Regulator
Lifecycle:
New from this manufacturer.
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