LTM4622
16
Rev F
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APPLICATIONS INFORMATION
A graphical representation of the aforementioned ther-
mal resistances is given in Figure7; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule. For example, in nor-
mal board-mounted applications, never does 100% of
the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
of the µModule—as the standard defines for θ
JCtop
and
θ
JCbottom
, respectively. In practice, power loss is ther-
mally dissipated in both directions away from the pack-
age—granted, in the absence of a heat sink and airflow,
a majority of the heat flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JSED51-12 to predict power loss heat flow and tempera-
ture readings at different interfaces that enable the cal-
culation of the JEDEC-defined thermal resistance values;
(3) the model and FEA software is used to evaluate the
µModule with heat sink and airflow; (4) having solved
for and analyzed these thermal resistance values and
simulated various operating conditions in the software
model, a thorough laboratory evaluation replicates the
simulated conditions with thermo-couples within a con-
trolled-environment chamber while operating the device
at the same power loss as that which was simulated. An
outcome of this process and due-diligence yields a set
of derating curves provided in other sections of this data
sheet. After these laboratory test have been performed
and correlated to the µModule model, then the θ
JB
and
θ
BA
are summed together to correlate quite well with the
µModule model with no airflow or heat sinking in a prop-
erly define chamber. This θ
JB
+ θ
BA
value is shown in the
Pin Configuration section and should accurately equal
the θ
JA
value because approximately 100% of power loss
Figure8. 1V Output Power Loss Figure9. 1.5V Output Power Loss Figure10. 2.5V Output Power Loss
OUTPUT CURRENT (A)
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3
1 2
4
12V
IN
5V
IN
OUTPUT CURRENT (A)
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3
1 2
4
12V
IN
5V
IN
OUTPUT CURRENT (A)
0
2.0
1.5
1.0
0.5
0
3
1 2
4
12V
IN
5V
IN
