ZL30704LDG6 Datasheet ZL30702LDG6, ZL30703LDG6, ZL30704LDG6 | P1-P3

Short Form Data Sheet

ZL30701/ZL30702/ZL30703/ZL30704

Confidential

ugust 2016

IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizer

Features

 Up to four independent clock channels

 Fully compliant to EEC (G.8262), SEC (G.813), GR-253

SMC and GR-1244 Stratum 3/3E

 Frequency accuracy performance for GSM, WCDMA-

FDD, LTE-FDD basestations and small cell applications,

with target performance less than ± 15 ppb.

 Frequency performance for ITU-T G.823 and G.824

synchronization interface, as well as G.8261 PNT EEC,

PNT PEC and CES interface specifications.

 Phase Synchronization performance for WCDMA-TDD,

TD-SCDMA, CDMA2000, LTE-TDD and LTE-A

applications with target performance less than ± 1 µs

phase alignment.

 Client holdover and reference switching between

multiple Servers



Support for new ITU-T packet clock recommendations

or drafts: G.8263 PEC-S, G.8273.2 T-BC, T-TSC,

G.8273.4 T-BC-P, T-TSC-P & T-TSC-A

 Excellent jitter performance of 180 fs rms (12 kHz to 20 MHz)

meets 10G/40G and 100G PHY jitter requirements

 Up to four programmable digital PLLs/NCOs with loop bandwidth

from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz

to 900 MHz

 Automatic hitless reference switching and digital holdover on

reference fail with initial holdover accuracy better than 0.1 ppb

 Any input reference can be fed with clock, sync (frame pulse),

clock /sync pair or clock modulated with sync pulse (embedded

PPS ePPS and embedded PP2S ePP2S)

Functional Block Diagram

Ordering Information

ZL30701LDG6* 100 Pin aQFN Trays

ZL30702LDG6* 100 Pin aQFN Trays

ZL30703LDG6* 100 Pin aQFN Trays

ZL30704LDG6* 100 Pin aQFN Trays

*Pb Free Tin/Silver/Copper

Package size: 10 x 10 mm

-40



C to +85



HP Synthesizer 2

Fs= Bs

*Ks

*Ms

/Ns

CML

LVCMOS

Div A

Clock Generator 2

Div B CML

LVCMOS

CML

LVCMOS

Div A

Clock Generator 3

Div B

CML

LVCMOS

HP Synthesizer 3

Fs= Bs

*Ks

*Ms

/Ns

Sys APLL

HPOUT4_2P

HPOUT5_2N

HPOUT6_3P

HPOUT7_3N

HPOUT8_4P

HPOUT9_4N

HPOUT10_5P

HPOUT11_5N

Div C

Div D

Reference Monitors

State Machine

Configuration

and Status

JTAG

ZL30701/ZL30702/ZL30703/ZL30704

One Diff / Two

Single Ended

REFIN0_0P

REFIN1_0N

JTAG

GPIO

SPI / I

PWR_b

DPLL0

Select Loop band.,

Phase slope limit

HP Synthesizer 1

Fs= Bs

*Ks

*Ms

/Ns

CML

2 x LVCMOS

Div A

Clock Generator 1

Div B

Div C

Div D

DPLL1

Select Loop band.,

Phase slope limit

DPLL2

Select Loop band.,

Phase slope limit

One Diff / Two

Single Ended

One Diff / Two

Single Ended

One Diff / Two

Single Ended

One Diff / Two

Single Ended

CML

2 x LVCMOS

Osc

SysClk

GP Synthesizer 0

Fs= Bs

*Ks

*Ms

/Ns

LVCMOS

Div A

Clock Generator 0

Div B

LVCMOS

GPOUT1

GPOUT0

Master Clock

OSCI

OSC0

Osc

MCLKIN_P

MCLKIN_N

REFIN2_1P

REFIN3_1N

REFIN4_2P

REFIN5_2N

REFIN6_3P

REFIN7_3N

REFIN8_4P

REFIN9_4N

HPOUT0_0P

HPOUT1_0N

HPOUT2_1P

HPOUT3_1N

PACKET_REF[0:3]

DPLL3

Select Loop band.,

Phase slope limit

PartNumber

ZL30701

ZL30702

ZL30703

ZL30704

AvailableDPLLs

DPLL[0]

DPLL[0,1]

DPLL[0,1,2]

DPLL[0,1,2,3]

Short Form Data Sheet

ZL30701/ZL30702/ZL30703/ZL30704

Confidential

ugust 2016

2 Feature List

2.1 General features

 Up to four independent clock channels

 Operates from a single crystal resonator or clock oscillator

o Supports split XO mode for low-frequency stability TCXO/OCXO with ultra-low jitter clock outputs

 Configurable from SPI/I2C bus or from pre-configured flash memory

2.2 Electrical Clock Inputs

 Acceptsupto10LVCMOSor5LVDS/HCSL/LVPECL/CMLinputs

 Frequencies from 0.5 Hz to 180 MHz for LVCMOS

 Frequencies from 0.5 Hz to 900 MHz for LVDS/HCSL/LVPECL/CML

 Flexible input reference monitoring automatically disqualifies references based on frequency and phase

irregularities.

o Each input reference has its own set of monitors which can be independently programmed.

o Loss of signal (LOS)

o Single Cycle Monitor (Triggers on glitches or variation in duty-cycle)

o Coarse Frequency Monitor

o Precise Frequency Monitor

 Locks to gapped clocks

2.3 Electrical Clock Input-Output Special Formats

 Supports 64 kHz composite clocks with external glue logic

 Supports embedded pulse per second (ePPS) single wire for carrying high-speed clock & 1PPS

 Supports REF-SYNC pair, a combination of a high speed clock reference and a frame pulse sync pair

 Each output can generate clock, sync pulse, embedded pulse per second (ePPS) or embedded pulse per 2

seconds (ePP2S)

o Clock modulated sync feature helps in reducing number of clock lines on backplane and in

addition provides equal delay for both clock and sync signals.

2.4 Electrical Clock Engine

 Digital PLLs filter jitter from 0.1 mHz up to 470 Hz

 Multiple modes of operation

o Freerun

o Forced holdover

o Forced reference

o Automatic

o NCO

 Internal state machine automatically controls state

o Locked

o Acquiring

o Holdover

 Automatic hitless reference switching and digital holdover on reference fail

o Physical-to-physical reference switching

o Physical-to-packet reference switching

o Packet-to-physical reference switching

o Packet-to-packet reference switching

 Support for fast lock with lock times in seconds

 Support for hitless reference switching

 Internal, per DPLL, time of day counters maintaining full 48-bit seconds and 32-bit nanoseconds aligned to

1PPS rollover

 Holdover better than 0.01 ppb

 Full rate conversion between input and output clock frequencies

 Supports ITU-T G.823, G.824 and G.8261 for 2048 Kbit/s and 1544 Kbit/s interfaces

 Supports G.781 SETS

Short Form Data Sheet

ZL30701/ZL30702/ZL30703/ZL30704

Confidential

ugust 2016

2.5 Electrical Clock Engine: Industry Specifications

 Support for wide variety of Equipment Clock specifications

o SyncE

 ITU-T G.8262 option 1 EEC (Europe/China)

 ITU-T G.8262 option 2 (USA)

o SONET/SDH

 ITU-T G.813 option 1 SEC (Europe/China)

 ITU-T G.813 option 2 (USA)

 ANSI T1.105/Telcordia GR-253 Stratum 3 for SONET

 Telcordia GR-253 SMC

o PDH

 ITU-T G.812 Type I SSU

 ITU-T G.812 Type II, ANSI T1.101/Telcordia GR-1244 Stratum 2 (without optional freq

monitoring at 16 ppb)

 ITU-T G.812 Type III, ANSI T1.101/Telcordia GR-1244 Stratum 3E

 ANSI T1.101/Telcordia GR-1244 Stratum 3

 ANSI T1.101/Telcordia GR-1244 Stratum 4E/4

2.6 Electrical Clock Generation

 Four programmable synthesizers

 Precision Synthesizers

o Each ultra-low jitter output can be independently set to be differential (CML) or two CMOS

o Six CML outputs

 Generate clock rates from 0.5 Hz to 900 MHz

 Jitter performance of 180 fs rms (12 KHz – 20 MHz)

 Meets OC-192, STM-64, 1 GbE & 10 GbE interface jitter requirements

o Twelve LVCMOS outputs

 Generate clock rates from 0.5 Hz to 180 MHz

 Jitter performance of 290 fs rms (12 kHz – 20 MHz)

 General Synthesizer

o Two LVCMOS outputs

o Generate clock rates from 1 Hz to 180 MHz

o Jitter performance of 17 ps rms (12 kHz – 20 MHz)

 Programmable output advancement/delay to accommodate trace delays or compensate for system routing

paths

 Each output has its own power supply pin which can be hooked to 3.3V, 2.5V or 1.8V supplies. Outputs may

be disabled to save power

2.7 Packet Synchronization

The Time Synchronization Algorithm is suitable for use in a wide variety of markets and applications, including the

following IEEE 1588-2008 Profiles

 Annex J.3 Delay Request-Response Default Profile

 Annex J.4 Peer-to-peer Default Profile

 ITU-T G.8265.1 Telecom Profile for Frequency Synchronization

 ITU-T G.8275.1 Telecom Profile for Phase with Full Timing Support Networks

 ITU-T G.8275.2 Telecom Profile for Phase with Partial Timing Support Networks

 CableLabs CM-SP-RDTI Remote DTI Profile

 SMPTE ST-2059-2 Professional Broadcast Environment Profile

 IEEE C37.238 Standard Profile for Use of IEEE 1588 Precision Time Protocol in Power System Applications.

 IEC 61850-9-3 Power Utility Automation Profile

 IEEE802.1as AVB-TSN gPTP

 IEEE 1588-2018 Annex X High Accuracy Profile (based on White Rabbit)

 IETF TICTOC Enterprise Profile

P1-P3 P4-P6

ZL30704LDG6

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Buy ZL30704LDG6

Manufacturer:

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Clock Generators & Support Products

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ZL30704LDG6

ZL30704LDG6

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