ZL30704LDG6 Datasheet ZL30702LDG6, ZL30703LDG6, ZL30704LDG6 | P4-P6

Short Form Data Sheet

ZL30701/ZL30702/ZL30703/ZL30704

Confidential

ugust 2016

2.7.1 Applications

The Time Synchronization Algorithm is suitable for many end application targets.

 Frequency accuracy performance for GSM, WCDMA-FDD, LTE-FDD femtocell, small cell (residential, urban,

rural, enterprise), picocell and macrocell applications, with target performance less than ± 15 ppb.

 Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT EEC,

PNT PEC and CES interface specifications.

 Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA, CDMA2000, LTE-TDD

and LTE-A femtocell, small cell (residential, urban, rural, enterprise), picocell and macrocell applications with

target performance less than ± 1 s phase alignment.

 Time Synchronization for TAI, UTC-traceability and GNSS/GPS replacement.

2.7.2 Packet Networks

The Time Synchronization Algorithm is suitable for high performance over a variety of packet networks

 ITU-T G.8261 Appendix VI

 ITU-T G.8261.1 network limit compliant

 ITU-T G.8271.1 network limit compliant

 ITU-T G.8271.2 (draft) network limit compliant

 Native Ethernet (switched) & IP (routed) networks

 xDSL

 Microwave

 Fully aware, partially aware and unaware timing supported networks

 Networks including intermediate Boundary Clocks and Transparent Clocks

 Networks with and without SyncE or frequency physical layer support

2.7.3 Clock Specifications

The Time Synchronization Algorithm is suitable to address a variety of standardized clock specifications, including

 ITU-T G.8263 PEC-S

 ITU-T G.8273.2 T-BC full on-path without SyncE

 ITU-T G.8273.2 T-BC full on-path with SyncE

 ITU-T G.8273.2 T-TSC full on-path without SyncE

 ITU-T G.8273.2 T-TSC full on-path with SyncE

 ITU-T G.8273.4 T-BC-P (draft)

 ITU-T G.8273.4 T-TSC-A (draft)

 ITU-T G.8273.4 T-TSC-P (draft)

2.7.4 Monitoring & Redundancy

The Time Synchronization Algorithm includes monitoring & redundancy for high availability synchronization, including

 Synchronization to the best available Server

 Client monitoring of secondary Server references

o Monitoring includes full time synchronization reporting of secondary Server

o Supports a programmable number of secondary Server connections

 Hitless reference switching between multiple Servers

 Holdover when Server packet connectivity is lost

 TIE clear option to build out, or clear, phase offsets between Server references

2.7.5 General

The Time Synchronization Algorithm includes many advanced features to aide in the high-accuracy & high-stability

applications, including

 Full PLL state machine (Freerun, Holdover, Frequency Lock Acquiring, Frequency Lock Acquired, Phase

Lock Acquired), with programmable thresholds for state transitions

 Programmable bandwidth configurability from sub-mHz to 100’s of mHz.

 Programmable packet rates from 1 packet/second to over 128 packets/second

 User ability to manually add frequency offsets due to temperature or ageing (especially during holdover state)

Short Form Data Sheet

ZL30701/ZL30702/ZL30703/ZL30704

Confidential

ugust 2016

3 Application Examples

The only difference between ZL30701/ZL30702/ZL30703/ZL30704 is the number of DPLLs. The least significant digit

in the part number assigns the number of available DPLLs.

3.1 Packet Layer - Centralized Architecture

A typical ZL30701/ZL30702/ZL30703/ZL30704 application is IEEE1588 time synchronization with centralized

architecture shown in Figure 2 . The application has three distinct modules: Ethernet PHY/MAC with timestamp

capability, Host processor running IEEE1588 protocol and Microsemi Time Sync Frequency and Phase algorithm and

the ZL30701/ZL30702/ZL30703/ZL30704 Synchronous Ethernet and IEEE1588 Packet Clock Network Synchronizer.

Although Figure 2 shows a single board application commonly known as “Pizza Box”, the same type of architecture

would be used in shelf based systems. Shelf based systems would have ZL30701/ZL30702/ZL30703/ZL30704

populated on active and redundant timing card and Ethernet PHY/MACs would be placed on line cards.

IEEE1588 Time Synchronization with Centralized Architecture

4 Product Family

There are several devices within the ZL30701/702/703/704 family. They are differentiated by the number of DPLL, as

shown in

Table 1 · ZL3070x Product Family

Product Number Number of DPLL Channels Number of Synthesizers

ZL30701 1 4

ZL30702 2 4

ZL30703 3 4

ZL30704 4 4

Short Form Data Sheet

ZL30701/ZL30702/ZL30703/ZL30704

Confidential

ugust 2016



Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and

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Products include high-performance and radiation-hardened analog mixed-signal integrated

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