11
Detailed Description
Theory of Operation
The HI5767 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 16 depicts
the circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal
1
and
2
, derived from the master sampling clock. During the
sampling phase,
1
, the input signal is applied to the sampling
capacitors, C
S
. At the same time the holding capacitors, C
H
,
are discharged to analog ground. At the falling edge of
1
the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase,
2
, the two bottom plates
of the sampling capacitors are connected together and the
holding capacitors are switched to the op-amp output nodes.
The charge then redistributes between C
S
and C
H
completing
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
differential output for the converter core. During the sampling
phase, the V
IN
pins see only the on-resistance of a switch and
C
S
. The relatively small values of these components result in a
typical full power input bandwidth of 250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a two-
bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital data
representing an analog input sample is output to the digital data
bus on the 7th cycle of the clock after the analog sample is
taken. This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following clock
cycle. The digital output data is synchronized to the external
sampling clock by a double buffered latching technique. The
digital output data is available in two’s complement or offset
binary format depending on the state of the Data Format Select
(DFS) control input (see Table 1, A/D Code Table).
Internal Reference Voltage Output, V
REFOUT
The HI5767 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is required.
V
REFOUT
must be connected to V
REFIN
when using the
internal reference voltage.
An internal band-gap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference
voltage used by the converter. A 4:1 array of substrate
PNPs generates the “delta-V
BE
” and a two-stage op-amp
closes the loop to create an internal +1.25V band-gap
reference voltage. This voltage is then amplified by a
wideband uncompensated operational amplifier connected
TABLE 1. A/D CODE TABLE
CODE CENTER
DESCRIPTION
DIFFERENTIAL
INPUT VOLTAGE
(V
IN
+ - V
IN
-)
OFFSET BINARY OUTPUT CODE
(DFS LOW)
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
M
S
B
L
S
B
M
S
B
L
S
B
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
+Full Scale (+FS) -
1
/
4
LSB
0.499756V 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+FS - 1
1
/
4
LSB 0.498779V 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0
+
3
/
4
LSB 732.422V 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
1
/
4
LSB -244.141V 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-FS + 1
3
/
4
LSB -0.498291V 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
-Full Scale (-FS) +
3
/
4
LSB
-0.499268V 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
NOTE:
4. The voltages listed above represent the ideal center of each output code shown with V
REFIN
= +2.5V.
HI5767
