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NB3N51032DTG

P1-P3P4-P6P7-P9P10-P12P13-P13
NB3N51032
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4
Table 5. MAXIMUM RATINGS (Note 2)
Symbol
Parameter Rating Unit
V
DD
Positive Power Supply with respect to GND (VDDXD and VDDODA) 4.6 V
V
I
Input Voltage with respect to GND (V
IN
) −0.5 V to V
DD
+0.5 V V
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm
500 lfpm
74
64
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) 50 °C/W
T
sol
Wave Solder 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 6. DC CHARACTERISTICS (V
DD
= 3.3 V ±5%, GND = 0 V, T
A
= −40°C to +85°C, Note 4)
Symbol
Characteristic Min Typ Max Unit
V
DD
Power Supply Voltage (VDDXD and VDDODA) 3.135 3.3 3.465 V
GND Power Supply Ground (GNDXD and GNDODA) 0 V
I
DD
Power Supply Current, 200 MHz Output, −0.75% spread 100 mA
I
DDOE
Power Supply Current when OE is Set Low 55 mA
V
IH
Input HIGH Voltage (X1/CLK, S0, S1, SS0, SS1 and OE) 2000 V
DD
+ 300 mV
V
IL
Input LOW Voltage (X1/CLK, S0, S1, SS0, SS1 and OE) GND − 300 800 mV
V
OH
Output HIGH Voltage for HCSL Output (Note 5) 660 850 mV
V
OL
Output LOW Voltage for HCSL Output (Note 5) −150 0 mV
V
cross
Crossing Voltage Magnitude (Absolute) for HCSL Output (Notes 6 and 7) 250 550 mV
DV
cross
Change in Magnitude of V
cross
for HCSL Output (Notes 6 and 8) 150 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. VDDXD and VDDODA power pins must be shorted to power supply voltage V
DD
and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken with outputs terminated with R
S
= 33.2 W, R
L
= 49.9 W, with test load capacitance of 2
pF and current biasing resistor set at 475 W. See Figure 9. Guaranteed by characterization.
5. Measurement taken from single−ended waveform.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx−.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
8. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx−. This is maximum allowed variance in the V
CROSS
for any particular system.
NB3N51032
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Table 7. AC CHARACTERISTICS (V
DD
= 3.3 V ±5%, GND = 0 V, T
A
= −40°C to +85°C; Note 9)
Symbol
Characteristic Min Typ Max Unit
f
CLKIN
Clock/Crystal Input Frequency 25 MHz
f
CLKOUT
Output Clock Frequency 25 200 MHz
F
NOISE
Phase−Noise Performance f
CLKOUT
= 100 Mhz
@ 100 Hz offset from carrier
@ 1 kHz offset from carrier
@ 10 kHz offset from carrier
@ 100 kHz offset from carrier
@ 1 MHz offset from carrier
@ 10 MHz offset from carrier
−88
−118
−131
−132
−144
−155
dBc/Hz
t
JITTER
Period Jitter Peak−to−Peak (Note 10) f
CLKOUT
= 200 Mhz
Period Jitter RMS (Note 10) f
CLKOUT
= 200 MHz
Cycle−Cycle RMS Jitter (Note 11) f
CLKOUT
= 200 MHz
Cycle−to−Cycle Peak to Peak Jitter (Note 11) f
CLKOUT
= 200 MHz
10
1.5
2.0
20
20
3.0
5.0
35
ps
t
JIT(
F
)
Phase RMS Jitter, Integration Range 12 kHz to 20 MHz 0.5 ps
f
MOD
Spread Spectrum Modulation Frequency 30 31.5 33 kHz
SSC
RED
Spectral Reduction, f
CLKOUT
of 100 MHz with −0.5% spread, 3
rd
Harmonic
(Note 12)
−10 dB
t
SKEW
Within Device Output to Output Skew 40 ps
Eppm Frequency Synthesis Error, All Outputs 0 ppm
t
SPREAD
Spread Spectruction Transition Time
(Stablization Time After Spread Spectrum Changes)
7 30 ms
t
OE
Output Enable/Disable Time (Note 13) 10
ms
t
DUTY_CYCLE
Output Clock Duty Cycle (Measured at cross point) 45 50 55 %
t
R
Output Risetime (Measured from 175 mV to 525 mV, Figure 11) 175 700 ps
t
F
Output Falltime (Measured from 525 mV to 175 mV, Figure 11) 175 700 ps
Dt
R
Output Risetime Variation (Single−Ended) 125 ps
Dt
F
Output Falltime Variation (Single−Ended) 125 ps
Stabilization
Time
Stabilization Time From Powerup V
DD
= 3.3 V 3.0 ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
9. VDDXD and VDDODA power pins must be shorted to power supply voltage V
DD
and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with R
S
= 33.2 W, R
L
= 49.9
W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 9. Guaranteed by characterization.
10.Sampled with 10000 cycles.
11. Sampled with 1000 cycles.
12.Spread spectrum clocking enabled.
13.Output pins are tri−stated when OE is asserted LOW. Output pins are driven differentially when OE is HIGH.
NB3N51032
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6
Table 8. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS,
V
DD
= 3.3 V ± 5%, T
A
= −40°C to 85°C
Symbol
Parameter Test Conditions Min Typ Max
PCIe
Industry
Spec
Unit
tj (PCIe Gen 1) Phase Jitter
Peak−to−Peak
(Notes 15
and 18)
f = 100 MHz, 25 MHz Crystal
Input Evaluation Band:
0 Hz − Nyquist (clock
frequency/2)
SSOFF 10 20
86 pS
SSON
(−0.5%)
19 28
tREFCLK_HF_RMS
(PCIe Gen 2)
Phase Jitter
RMS (Notes 16
and 18)
f = 100 MHz, 25 MHz Crystal
Input High Band:
1.5 MHz − Nyquist (clock
frequency/2)
SSOFF 1.0 1.8
3.1 pS
SSON
(−0.5%)
1.1 1.9
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS (Notes 16
and 18)
f = 100 MHz, 25 MHz Crystal
Input Low Band:
10 kHz − 1.5 MHz
SSOFF 0.1 0.15
3 pS
SSON
(−0.5%)
0.8 1.1
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS (Notes 17
and 18)
f = 100 MHz, 25 MHz Crystal
Input Evaluation Band: 0 Hz −
Nyquist (clock frequency/2)
SSOFF 0.35 0.7
1 pS
SSON
(−0.5%)
0.55 0.8
14.Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
15.Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps
peak−to−peak for a sample size of 10
6
clock periods.
16.RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the
worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for t
REFCLK_HF_RMS
(High Band)
and 3.0 ps RMS for t
REFCLK_LF_RMS
(Low Band).
17.RMS jitter after applying system transfer function for the common clock architecture.
18.VDDXD and VDDODA power pins must be shorted to power supply voltage V
DD
and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with R
S
= 33.2 W, R
L
= 50 W,
with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 11. This parameter is guaranteed by characterization.
Not tested in production.
P1-P3P4-P6P7-P9P10-P12P13-P13

NB3N51032DTG

Mfr. #:
Buy NB3N51032DTG
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products 3.3 V, CRYSTAL TO 25 MHZ,
Lifecycle:
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