10
LT1676
APPLICATIONS INFORMATION
WUU
U
Power loss internal to the LT1676 related to actual output
current is composed of both DC and AC switching losses.
These can be roughly estimated as follows:
DC switching losses are dominated by output switch “ON
voltage”, i.e.,
P
DC
= V
ON
• I
OUT
• DC
V
ON
= Output switch ON voltage, typically 1V at 500mA
I
OUT
= Output current
DC = ON duty cycle
AC switching losses are typically dominated by power lost
due to the finite rise time and fall time at the V
SW
node.
Assuming, for simplicity, a linear ramp up of both voltage
and current and a current rise/fall time equal to 15ns,
P
AC
= 1/2 • V
IN
• I
OUT
• (t
r
+ t
f
+ 30ns) • f
t
r
= (V
IN
/1.6)ns in high dV/dt mode
(V
IN
/0.16)ns in low dV/dt mode
t
f
= (V
IN
/1.6)ns (irrespective of dV/dt mode)
f = switching frequency
Total power dissipation of the die is simply the sum of
quiescent, DC and AC losses previously calculated.
P
D(TOTAL)
= P
Q
+ P
DC
+ P
AC
Frequency Compensation
Loop frequency compensation is performed by connect-
ing a capacitor, or in most cases a series RC, from the
output of the error amplifier (V
C
pin) to ground. Proper
loop compensation may be obtained by empirical meth-
ods as described in detail in Application Note 19. Briefly,
this involves applying a load transient and observing the
dynamic response over the expected range of V
IN
and
I
LOAD
values.
As a practical matter, a second small capacitor, directly
from the V
C
pin to ground is generally recommended to
attenuate capacitive coupling from the V
SW
pin. A typical
value for this capacitor is 100pF. (See Switch Node Con-
siderations).
Switch Node Considerations
For maximum efficiency, switch rise and fall times are
made as short as practical. To prevent radiation and high
oscillator frequency during short-circuit conditions can
then maintain control with the effective minimum ON time.
A further potential problem with short-circuit operation
might occur if the user were operating the part with its
oscillator slaved to an external frequency source via the
SYNC pin. However, the LT1676 has circuitry that auto-
matically disables the sync function when the oscillator is
slowed down due to abnormally low FB voltage.
Feedback Divider Considerations
An LT1676 application typically includes a resistive divider
between V
OUT
and ground, the center node of which drives
the FB pin to the reference voltage V
REF
. This establishes
a fixed ratio between the two resistors, but a second
degree of freedom is offered by the overall impedance
level of the resistor pair. The most obvious effect this has
is one of efficiency—a higher resistance feedback divider
will waste less power and offer somewhat higher effi-
ciency, especially at light load.
However, remember that oscillator slowdown to achieve
short-circuit protection (discussed above) is dependent
on FB pin behavior, and this in turn, is sensitive to FB node
external impedance. Figure 2 shows the typical relation-
ship between FB divider Thevenin voltage and impedance,
and oscillator frequency. This shows that as feedback
network impedance increases beyond 10k, complete os-
cillator slowdown is not achieved, and short-circuit pro-
tection may be compromised. And as a practical matter,
the product of FB pin bias current and larger FB network
impedances will cause increasing output voltage error.
(Nominal cancellation for 10k of FB Thevenin impedance
is included internally.)
Thermal Considerations
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The packages are rated at 110°C/W
for the 8-pin SO (S8) and 130°C/W for 8-pin PDIP (N8).
Quiescent power is given by:
P
Q
= I
VIN
• V
IN
+ I
VCC
• V
OUT
(This assumes that the V
CC
pin is connected to V
OUT
.)
