4
LT1676
TYPICAL PERFORMANCE CHARACTERISTICS
UW
SHDN Pin Shutdown Threshold
vs Temperature
TEMPERATURE (°C)
–50
900
800
700
600
500
400
300
200
25 75
LT1676 G04
–25 0
50 100 125
SHDN PIN VOLTAGE (mV)
TEMPERATURE (°C)
–50
1.30
1.28
1.26
1.24
1.22
1.20
25 75
LT1676 G06
–25 0
50 100 125
SHDN PIN VOLTAGE (V)
UPPER THRESHOLD
LOWER THRESHOLD
SHDN PIN VOLTAGE (V)
0
SHDN PIN INPUT CURRENT (µA)
5
0
–5
–10
–15
–20
4
1676 G05
1
2
3
5
25°C
–55°C
125°C
SHDN Pin Input Current
vs Voltage
SHDN Pin Lockout Thresholds
vs Temperature
TEMPERATURE (°C)
SWITCH MINIMUM ON-TIME (ns)
600
500
400
300
200
100
0
1676 G09
–50 25 75
–25 0
50 100 125
V
IN
= 48V
R
L
= 50
FB =
TEMPERATURE (°C)
SWITCHING FREQUENCY (kHz)
106
104
102
100
98
96
94
1676 G07
–50 25 75
–25 0
50 100 125
TEMPERATURE (°C)
MINIMUM SYNCHRONIZATION VOLTAGE (V)
2.25
2.00
1.75
1.50
1.25
1.00
0.75
1676 G08
–50 25 75
–25 0
50 100 125
Switching Frequency
vs Temperature
Switch Minimum On-Time
vs Temperature
Minimum Synchronization Voltage
vs Temperature
V
C
Pin Switching Threshold,
Boost Threshold, Clamp Voltage
vs Temperature
TEMPERATURE (°C)
–50
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
25 75
LT1676 G10
–25 0
50 100 125
V
C
PIN VOLTAGE (V)
CLAMP
VOLTAGE
BOOST
THRESHOLD
SWITCHING
THRESHOLD
FB PIN VOLTAGE (V)
1.0
FEEDBACK AMPLIFIER OUTPUT CURRENT (µA)
100
50
0
–50
100
150
1.4
1676 G11
1.1
1.2
1.3
1.5
25°C
–55°C
125°C
Error Amplifier Transconductance
vs Temperature
Feedback Amplifier Output
Current vs FB Pin Voltage
TEMPERATURE (°C)
–50
750
700
650
600
550
500
450
400
25 75
LT1676 G12
–25 0
50 100 125
TRANSCONDUCTANCE (µmho)
5
LT1676
PIN FUNCTIONS
UUU
SHDN (Pin 1):
When pulled below the shutdown mode
threshold, nominally 0.30V, this pin turns off the regula-
tor and reduces V
IN
input current to a few tens of micro-
amperes (shutdown mode).
When this pin is held above the shutdown mode thresh-
old, but below the lockout threshold, the part will be
operational with the exception that output switching
action will be inhibited (lockout mode). A user-adjustable
undervoltage lockout can be implemented by driving this
pin from an external resistor divider to V
IN
. This action is
logically “ANDed” with the internal UVLO, set at nominally
6.7V, such that minimum V
IN
can be increased above
6.7V, but not decreased (see Applications Information).
If unused, this pin should be left open. However, the high
impedance nature of this pin renders it susceptible to
coupling from the high speed V
SW
node, so a small
capacitor to ground, typically 100pF or so is recom-
mended when the pin is left “open.”
V
CC
(Pin 2): This pin is used to power the internal control
circuitry off of the switching supply output. Proper use of
this pin enhances overall power supply efficiency. During
start-up conditions, internal control circuitry is powered
directly from V
IN
. If the output capacitor is located more
than an inch from the V
CC
pin, a separate 0.1µF bypass
capacitor to ground may be required right at the pin.
V
SW
(Pin 3): This is the emitter node of the output switch
and has large currents flowing through it. This node
moves at a high dV/dt rate, especially when in “boost”
mode. Keep the traces to the switching components as
short as possible to minimize electromagnetic radiation
and voltage spikes.
GND (Pin 4): This is the device ground pin. The internal
reference and feedback amplifier are referred to it. Keep
the ground path connection to the FB divider and the V
C
compensation capacitor free of large ground currents.
V
IN
(Pin 5): This is the high voltage supply pin for the
output switch. It also supplies power to the internal control
circuitry during start-up conditions or if the V
CC
pin is left
open. A high quality bypass capacitor that meets the input
ripple current requirements is needed here. (See Applica-
tions Information.)
SYNC (Pin 6): Pin used to synchronize internal oscillator
to the external frequency reference. It is directly logic
compatible and can be driven with any signal between
10% and 90% duty cycle. The sync function is internally
disabled if the FB pin voltage is low enough to cause
oscillator slowdown. If unused, this pin should be grounded.
FB (Pin 7): This is the inverting input to the feedback
amplifier. The noninverting input of this amplifier is inter-
nally tied to the 1.24V reference. This pin also slows down
the frequency of the internal oscillator when its voltage is
abnormally low, e.g., 2/3 of normal or less. This feature
helps maintain proper short-circuit protection.
V
C
(Pin 8): This is the control voltage pin which is the
output of the feedback amplifier and the input of the
current comparator. Frequency compensation of the over-
all loop is effected by placing a capacitor, (or in most cases
a series RC combination) between this node and ground.
SWOFF
1676 TD01
BOOST
SWON
SWDR
0
V
IN
V
SW
SWOFF
1676 TD02
BOOST
SWON
SWDR
0
V
IN
V
SW
High dV/dt Mode Low dV/dt Mode
TIMING DIAGRAMS
WUW
6
LT1676
BLOCK DIAGRA
W
SWDR
SWDR
SWON
SWON
BOOST
1676 BD
BOOST
SWOFF
SWOFF
LOGICOSC
BIAS
V
TH
V
B
V
BG
V
BG
FB
V
C
GND
SYNC
SHDN
V
CC
FB
AMP
BOOST
COMP
gm
I
I
I I
R1 R
SENSE
I
COMP
Q4
Q3
Q2
Q1
Q5
V
SW
D1
V
IN
5
3
2
1
6
4
8
7
OPERATIO
U
The LT1676 is a current mode switching regulator IC that
has been optimized for high efficiency operation in high
input voltage, low output voltage Buck topologies. The
Block Diagram shows an overall view of the system.
Several of the blocks are straightforward and similar to
those found in traditional designs, including: Internal Bias
Regulator, Oscillator and Feedback Amplifier. The novel
portion includes an elaborate Output Switch section and
Logic Section to provide the control signals required by
the switch section.
The LT1676 operates much the same as traditional
current mode switchers, the major difference being its
specialized output switch section. Due to space con-
straints, this discussion will not reiterate the basics of
current mode switcher/controllers and the “Buck” topol-
ogy. A good source of information on these topics is
Application Note 19.
Output Switch Theory
One of the classic problems in delivering low output
voltage from high input voltage at good efficiency is that
minimizing AC switching losses requires very fast volt-
age (dV/dt) and current (dI/dt) transition at the output
device. This is in spite of the fact that in a bipolar
implementation, slow lateral PNPs must be included in
the switching signal path.
Fast positive-going slew rate action is provided by lateral
PNP Q3 driving the Darlington arrangement of Q1 and Q2.
The extra β available from Q2 greatly reduces the drive
requirements of Q3.
Although desirable for dynamic reasons, this topology
alone will yield a large DC forward voltage drop. A second
lateral PNP, Q4, acts directly on the base of Q1 to reduce
the voltage drop after the slewing phase has taken place.
To achieve the desired high slew rate, PNPs Q3 and Q4 are
“force-fed” packets of charge via the current sources
controlled by the boost signal.

LT1676IS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Wide In Rng, Hi Eff, Buck Sw Reg
Lifecycle:
New from this manufacturer.
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