3
2006 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1112
retemaraPlobmySsnoitidnoCniMpyTxaMstinU
).tnoC(snoitceSraeniL
TTVegatloVtuptuO)A2111CS(
TTV
2.1
I
O
WOL=LESTTV,A2ot0=671.1002.1422.1V
)2111CS(
TTV
52.1
I
O
WOL=LESTTV,A2ot0=522.1052.1572.1
TTV
5.1
I
O
HGIH=LESTTV,A2ot0=074.1005.1035.1V
PGAegatloVtuptuOPGA
5.1
I
O
WOL=LESPGA,A2ot0=074.1005.1035.1V
PGA
3.3
I
O
HGIH=LESPGA,A2ot0=432.3003.3V
JDAegatloVtuptuOJDAI
O
A2ot0=%2-)BR/AR+1(*2.1%2+V
tnerruCsaiBNESTTV
)2111CS(
saibI
NESTTV
09021041Aµ
tnerruCsaiBNESTTV
)A2111CS(
saibI
NESTTV
15Aµ
tnerruCsaiBNESPGAsaibI
NESPGA
011051071Aµ
tnerruCsaiBNESJDAsaibI
NESJDA
15Aµ
tnerruCetaGTTVecruosI
etagTTV
V0.3=etagV,V57.4=YBTSV5005Aµ
knisI
etagTTV
005Aµ
tnerruCetaGPGAecruosI
etagPGA
V0.3=etagV,V57.4=YBTSV5005Aµ
knisI
etagPGA
005Aµ
tnerruCetaGJDAecruosI
etagJDA
V0.3=etagV,V57.4=YBTSV5005Aµ
knisI
etagJDA
005Aµ
noitalugeRdaoLDAOL
GER
I,V03.3=NITTV
O
A2ot0=3.0%
noitalugeReniLENIL
GER
,V74.3otV31.3=NITTV
A2=oI
3.0%
)LOA(niaG
)2(
NIAG
ODL
ETAGottuptuOSODL05Bd
Electrical Characteristics (Cont.)
Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; T
A
= 25°C
Notes:
(1) All electrical characteristics are for the application circuit on page 19.
(2) Guaranteed by design
(3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until
regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions.
(4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTIN
TH
(1.5V). During the glitch
timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit
protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip
threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input
voltage or the 5VSTBY is cycled.
(5) PWRGD pin is kept low during the power up, until the VTT output has reached its PG
td1.2
or PG
td1.5
level. At that time the PWRGD
source current I
PG
(20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the
capacitor is charged above the PG
Delay_TH
(1.5V), the PWRGD pin is released from ground.