16 2006 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1112
Theory Of Operation
The SC1112 was designed for the latest high speed mother
boards requiring a controlled power up sequencing of
the Outputs, and a programmable delay for the Power
good signal.
Three Linear controllers have been incorporated into the
SC1112. The VTT output can be programmed to either a
1.250V or a 1.500V by applying a LOW or a HIGH control
signal to the VTTSEL pin. AGP output can also be pro-
grammed via AGPSEL pin to a 1.50V or a 3.30V. The
SC1112 also provides an Adjustable output which utilizes
a resistive voltage divider.
The +5VSTBY supply will power the internal Reference,
Charge Pump, Oscillator, and the Fet controllers. After
the +5VSTBY has been established, LDO outputs will track
the VTTIN (3.30V) supply as it is applied.
An external capacitor connected to the Delay pin will pro-
gram the VTT short circuit delay time (SC
td
), and the PWRGD
delay time (PG
td
).
During power up, an internal short circuit glitch timer will
start once the VTT Input Voltage exceeds the VTTIN
TH
(1.5V).
During the glitch timer immunity time, determined by the
Delay capacitor (Delay time is approximately equal to
(Cdelay*SCTH)/ISC), the short circuit protection is disabled
to allow VTT output to rise above the trip threshold (0.7V).
If the VTT output has not risen above the trip threshold
after the immunity time has elapsed, the VTT output is
latched off and will only be enabled again if either the VTT
input voltage or the 5VSTBY is cycled.
PWRGD pin is kept low during the power up, until the VTT
output has reached its PG
td1.25
or PG
td1.5
level. At that time
the PWRGD source current I
PG
(20uA) is enabled and will
start charging the external PWRGD delay capacitor
connected to the DELAY pin. Once the capacitor is charged
above the PG
Delay_TH
(1.5V), the PWRGD pin is released from
ground. A detailed timing diagram is shown on pages 4 to
5.
Also included is an overcurrent protection circuit that
monitors the VTT voltage. If the output voltage drops
below 700mV, as would occur during an overcurrent or
short condition, the device will pull the drive pin low and
latch off the output.
Fixed Output Voltage Options (VTT, AGP)
Please refer to the Application Circuit on Page 1. The VTT
and the AGP fixed output voltage can be programed from
a Control logic signal. Table below shows the possible
voltages:
LESTTVLESPGATTVPGA
00 V52.1V05.1
01 V52.1V03.3
10 V05.1V05.1
11 V05.1V03.3
Once the VTTSEL or the AGPSEL signal is established, an
internal resistive divider is used to compare the bandgap
reference voltage with the feedback output voltage. The
drive pin voltage is then adjusted to
maintain the output voltage set by the internal resistor
divider. Referring to the block diagram on page 8.
It is possible to adjust the output voltage of the VTT or
AGP, by applying an external resistor divider to the sense
pin (please refer to Figure 1 on Page 17). Since the sense
pin sinks a nominal 100µA, the resistor
values should be selected to allow 10mA to flow through
the divider. This will ensure that variations in this current
do not adversely affect output voltage regulation. Thus a
target value for R2 (maximum) can be calculated:
Ω≤
mA10
V
2R
)FIXED(OUT
The output voltage can only be adjusted upwards from
the fixed output voltage, and can be calculated using the
following equation:
VoltsA1001R
2R
1R
1VV
)FIXED(OUT)ADJUSTED(OUT
µ•+
+•=
Applications Infomation
