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www.fairchildsemi.com
FDG901D Rev. E
FDG901D Slew Rate Control IC for P-Channel MOSFETs
Application Information
Typical Application
Battery powered systems make extensive usage of load
switching, turning the power to subsystems off, in order to
extend battery life. Power MOSFETs are used to accomplish
this task. In PDA's and Cell phones, these MOSFETs are
usually low threshold P-Channels. Since the loads typically
include bypass capacitor components (high capacitive
component), a high inrush current can occur when the load is
switched on. This inrush current can cause transients on the
main power supply disturbing circuitry supplied by it.
The simplest method of limiting the inrush current is to control
the slew rate of the MOSFET switch. This can be done with
external R/C circuits, but this approach can occupy significant
PCB area, and involves other compromises in performance.
The slew rate control driver IC FDG901D is specifically
designed to interface low voltage digital circuitry with power
MOSFETs and reduce the rapid inrush current in load switch
applications. The IC limits inrush current by controlling the
current, which drives the gate of the P-Channel MOSFET
switch.
The control input is a CMOS compatible input with a minimum
high input voltage of 2.55V with a power rail voltage of 6V.
Therefore, it is compatible with any CMOS logic voltages
between 2.55V and 5V and under these conditions there is no
additional configuration required.
The Slew Rate Control Driver (FDG901D) is designed to give a
programmed choice of one of three steady dv/dt states on the
output during turn-on. To change the dv/dt value, the user
needs to use the Slew Rate Control Pin (Pin 2). To utilize the
smallest current setting ( 10 nA) from the IC, a voltage equal to
V
DD
must be applied to the Slew Rate Control Pin 2. To use the
next higher current setting ( ~1A) a voltage equal to Ground
must be applied to Pin 2. To achieve the highest current setting
( ~80A) or obtain a faster switching speed, the Slew Rate Pin2
must be open (floating). A higher value of capacitance will
result in a slower switching rate. To determine the switching
times of each setting use the simple equation:
where Qg is the Gate charge in nC for a given MOSFET and IG
is the gate current controlled by the slew rate pin.
Below is a captured image from an oscilloscope depicting the
device response. The FDG901D was connected to control an
FDG258P P-Channel DMOS. The Slew Rate control pin was
set to open (floating state).
Load
Ig
Application Circuit
1
3
5
4
2
Slew Rate
Control
Logic
Signal
I
Source
Gate
Drain
VDD
Load
Ig
Application Circuit
1
3
5
4
2
Slew Rate
Control
Logic
Signal
I
Source
Gate
Drain
VDD
V
RLoad
V
gate
(inverted)
V
IN
Circuit w aveform s for an FDG901D controlling a P-Channel FDG 258 P MO FET
V
DD
= 5.5V
V
IN
= 5.5V
R
LOA D
= 1.5
V
RLoad
V
gate
(inverted)
V
IN
Circuit w aveform s for an FDG901D controlling a P-Channel FDG 258 P MO FET
V
RLoad
V
gate
(inverted)
V
IN
Circuit w aveform s for an FDG901D controlling a P-Channel FDG 258 P MO FET
V
DD
= 5.5V
V
IN
= 5.5V
R
LOA D
= 1.5
