LTC690/LTC691
LTC694/LTC695
10
690ff
For more information www.linear.com/690
applicaTions inForMaTion
These products provide BATT ON output to drive the base
of external PNP transistor (Figure 2). If higher currents
are needed with the LTC690 and LTC694, a high current
Schottky diode can be connected from the V
CC
pin to the
V
OUT
pin to supply the extra current.
5V
3V
0.1µF
0.1µF
V
BATT
V
CC
LTC691
LTC695
V
OUT
GND
4
3
1
2
5
ANY PNP POWER TRANSISTOR
690 F02
BATT ON
The LTC690 family is protected for safe area operation
with short-circuit limit. Output current is limited to ap-
proximately 200mA. If the device is overloaded for long
period of time, thermal shutdown turns the power switch
off until the device cools down. The threshold temperature
for thermal shutdown is approximately 155°C with about
10°C of hysteresis which prevents the device from oscil-
lating in and out of shutdown.
The PNP switch used in competitive devices was not chosen
for the internal power switch because it injects unwanted
current into the substrate. This current is collected by the
V
BATT
pin in competitive devices and adds to the charging
current of the battery which can damage lithium batteries.
The LTC690 family uses a charge pumped NMOS power
switch to eliminate unwanted charging current while
achieving low dropout and low supply current. Since no
current goes to the substrate, the current collected by
V
BATT
pin is strictly junction leakage.
A 125Ω PMOS switch connects the V
BATT
input to V
OUT
in battery back-up mode. The switch is designed for very
low dropout voltage (input-to-output differential). This
feature is advantageous for low current applications such
as battery back-up
in CMOS RAM and other low power
CMOS
circuitry. The supply current in battery back-up
mode is 1µA maximum.
The operating voltage at the V
BATT
pin ranges from 2.0V
to 4.25V. High value capacitors, such as electrolytic or
farad-size double layer capacitors, can be used for short
term memory back-up instead of a battery. The charging
resistor for both capacitors and rechargeable batteries
should be connected to V
OUT
since this eliminates the
discharge path that exists when the resistor is connected
to V
CC
(Figure 3).
5V
3V
0.1µF
0.1µF
V
BATT
V
CC
LTC690
LTC691
LTC694
LTC695
V
OUT
GND
690 F03
V
OUT
– V
BATT
R
I =
R
Replacing the Back-Up Battery
When changing the back-up battery with system power
on, spurious resets can occur while battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge
up the stray capacitance on the V
BATT
pin. The oscillation
cycle is as follows: When V
BATT
reaches within 50mV of
V
CC
, the LTC690 switches to battery back-up. V
OUT
pulls
V
BATT
low and the device goes back to normal operation.
The leakage current then charges up the V
BATT
pin again
and the cycle repeats.
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, a resistor
from V
BATT
to GND will hold the pin low while changing
the battery. For example, the battery standby current is
A maximum over temperature and the external resistor
required to hold V
BATT
below V
CC
is:
R
V
CC
50mV
1µA
With V
CC
= 4.5V, a 4.3M resistor will work. With a 3V bat-
tery, this resistor will draw only 0.7µA from the battery,
which is negligible in most cases.
Figure 2. Using BATT ON to Drive External PNP Transistor
Figure 3. Charging External Battery Through V
OUT
LTC690/LTC691
LTC694/LTC695
11
690ff
For more information www.linear.com/690
applicaTions inForMaTion
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1µF capacitor are
recommended to prevent any overshoot beyond V
CC
due
to the lead inductance (Figure 4).
4.3M
0.1µF
V
BATT
LTC690
LTC691
LTC694
LTC695
GND
690 F04
10Ω
Figure 4. 10Ω/0.1µF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V
BATT
to GND and V
OUT
to V
CC
.
Memory Protection
The LTC691 and LTC695 include memory protection cir-
cuitry that ensures the integrity of the data in memory by
preventing write operations when V
CC
is at invalid level.
Tw o additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When V
CC
is 5V,
CE OUT follows CE IN with a typical propagation delay of
20ns. When V
CC
falls below the reset voltage threshold or
V
BATT
, CE OUT is forced high, independent of CE IN. CE
OUT is an alternative signal to drive the CE, CS, or Write
input of battery-backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM
application.
Memory
protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL STATUS
V
CC
C2 monitors V
CC
for active switchover.
V
OUT
V
OUT
is connected to V
BATT
through an internal PMOS switch.
V
BATT
The supply current is 1µA maximum.
BATT ON Logic high. The open-circuit output voltage is equal to V
OUT
.
PFI Power failure input is ignored.
PFO Logic low
RESET Logic low
RESET Logic high. The open-circuit output voltage is equal to V
OUT
.
LOWLINE Logic low
WDI Watchdog input is ignored.
WDO Logic high. The open-circuit output voltage is equal to V
OUT
.
CE IN ChipEnable Input is ignored.
CE OUT Logic high. The open-circuit output voltage is equal to V
OUT
.
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
V
CC
V1
CE IN
V
OUT
= V
BATT
CE OUT
V
OUT
= V
BATT
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
690 F05
Figure 5. Timing Diagram for CE IN and CE OUT
LTC690/LTC691
LTC694/LTC695
12
690ff
For more information www.linear.com/690
Power-Fail Warning
The LTC690 family generates a Power Failure Output (PFO)
for early warning of failure in the microprocessor’s power
supply. This is accomplished by comparing the Power
Failure Input (PFI) with an internal 1.3V reference. PFO
goes low when the voltage at the PFI pin is less than 1.3V.
Typically PFI is driven by an external voltage divider (R1 and
R2 in Figures 8 and 9) which senses either an unregulated
DC input or a regulated 5V output. The voltage divider ratio
can be chosen such that the voltage at the PFI pin falls
below 1.3V several milliseconds before the 5V supply falls
below the maximum reset voltage threshold 4.75V. PFO is
normally used to interrupt the microprocessor to execute
shutdown procedure between PFO and RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower
trip points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the sum-
ming junction at the PFI pin.
V
H
= 1.3V 1+
R1
R2
+
R1
R3
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
V
L
= 1.3V 1+
R1
R2
(5V 1.3V)R1
1.3V (R3 + R4)
Assuming R4 << R3,V
HYSTERESIS
= 5V
R1
R3
Example 1: The circuit in Figure 8 demonstrates the use
of the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of
the supply input V
IN
is 100mV/ms and the total time to
execute a shutdown procedure is 8ms. Also the noise of
V
IN
is 200mV. With these assumptions in mind, we can
reasonably set V
L
= 7.5V which 1.25V greater than the sum
of maximum reset voltage threshold and the dropout volt-
age of LT1086-5 (4.75V + 1.5V) and V
HYSTERESIS
= 850mV.
applicaTions inForMaTion
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V
3V
0.1µF
10µF
V
BATT
V
CC
LTC691
LTC695
V
OUT
GND
690 F06
V
CC
RESET
CE IN
CE OUT
RESET
0.1µF
TO µP
FROM DECODER
CS
20ns PROPAGATION DELAY
62512
RAM
GND
+
5V
3V
0.1µF
10µF
V
BATT
V
CC
LTC690
LTC694
V
OUT
GND
690 F07
V
CC
RESET
0.1µF
CS
62128
RAM
CS1
CS2
GND
+
10µF
100µF
V
IN
V
OUT
ADJ
690 F08
V
CC
0.1µF
TO µP
PFO
GND
LT1086-5
V
IN
≥ 7.5V
R4
10k
PFI
LTC690/LTC691
LTC694/LTC695
R1
51k
R2
10k
R3
300k
5V
++
10µF
10µF
V
IN
V
OUT
ADJ
1690 F09
0.1µF
TO µP
LT1086-5
V
IN
≥ 6.5V
R4
10k
R1
27k
R3
2.7M
R2
8.2k
5V
R5
3.3k
V
CC
GND
PFO
PFI
LTC690/LTC691
LTC694/LTC695
+ +
Figure 7. Write Protect for RAM with LTC690 or LTC694
Figure 8. Monitoring
Unregulated
DC Supply
with the LTC690’s Power-Fail Comparator
Figure 9. Monitoring
Regulated
DC Supply
with the LTC690’s Power-Fail Comparator

LTC690IS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits uP Supervisor with Watchdog
Lifecycle:
New from this manufacturer.
Delivery:
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