IDT8N3DV85CCD REVISION A OCTOBER 30, 2013 11 ©2013 Integrated Device Technology, Inc.
IDT8N3DV85 Data Sheet LVPECL DUAL-FREQUENCY PROGRAMMABLE VCXO
Parameter Measurement Information, continued
RMS Period Jitter
Applications Information
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 1A and 1B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 1A. 3.3V LVPECL Output Termination Figure 1B. 3.3V LVPECL Output Termination
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10
-7
)% of all measurements
Histogram
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
LVPECL Input
3.3V
3.3V
+
_
