C8051F00x/01x-DK
8 Rev. 0.6
6.5. Expansion I/O Connector (J2)
The
64
-pin expansion I/O connector J1 provides access to most signal pins of the
C8051F005
device on the target
board. A small through-hole prototyping area is also provided. All I/O signals routed to connector J2 are also routed to
through-hole connection points between J2 and the prototyping area (see
Figure 4 on page 9
).
The signal layout pat-
tern of these connection points is identical to the adjacent J2 connector pins
. See Table 5 for a list of pin descrip-
tions for J2
.
Table 5: J2 Pin Descriptions
Pin Description Pin Description
1 +VD (digital voltage supply) 28 P3.7
2XTAL1 29P3.4
3 P1.6 30 P3.5
4 P1.7 31 P3.2
5 P1.4 32 P3.3
6 P1.5 33 P3.0
7 P1.2 34 P3.1
8P1.3 36/RST
9 P1.0 39,41,42 GND (digital ground)
10 P1.1 45,47,63 GNDA (analog ground)
11 P0.6 46,64 +VA (analog voltage supply)
12 P0.7 48 DAC0
13 P0.4 49 CP1-
14 P0.5 50 DAC1
15 P0.2 51 CP1+
16 P0.3 52 CP0-
17 P0.0 53 VREF
18 P0.1 54 CP0+
19 P2.6 55 AIN0
20 P2.7 56 AIN1
21 P2.4 57 AIN2
22 P2.5 58 AIN3
23 P2.2 59 AIN4
24 P2.3 60 AIN5
25 P2.0 61 AIN6
26 P2.1 62 AIN7
27 P3.6
