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MC100EPT26DTR2G

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 17
1 Publication Order Number:
MC100EPT26/D
MC100EPT26
3.3V 1:2 Fanout Differential
LVPECL/LVDS to LVTTL
Translator
Description
The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are
used only +3.3 V and ground are required. The small outline 8-lead
package and the 1:2 fanout design of the EPT26 makes it ideal for
applications which require the low skew duplication of a signal in a
tightly packed PC board.
The V
BB
output allows the EPT26 to be used in a Single-Ended
input mode. In this mode the V
BB
output is tied to the D0 input for a
non-inverting buffer or the D0 input for an inverting buffer. If used,
the V
BB
pin should be bypassed to ground with > 0.01ĂmF capacitor.
For a Single-Ended direct connection, use an external voltage
reference source such as a resistor divider. Do not use V
BB
for a
Single-Ended direct connection or port to another device.
Features
• 1.4 ns Typical Propagation Delay
• Maximum Frequency = > 275 MHz Typical
• The 100 Series Contains Temperature Compensation
• Operating Range: V
CC
= 3.0 V to 3.6 V with GND = 0 V
• 24 mA TTL outputs
• Q Outputs Will Default LOW with Inputs Open or at V
EE
• V
BB
Output
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package
SOIC−8 NB
D SUFFIX
CASE 751−07
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R−02
ALYWG
G
KA26
1
8
1
8
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
1
8
KPT26
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping†
MC100EPT26DG SOIC−8 NB
(Pb-Free)
98 Units/Tube
MC100EPT26DR2G
2500 Tape & Reel
TSSOP−8
(Pb-Free)
MC100RPT26DTR2G 2500 Tape & Reel
MC100EPT26DTG 100 Tape & Reel
DFN8
(Pb-Free)
MC100EPT26MNR4G 1000 Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
SOIC−8 NB TSSOP−8 DFN8
SOIC−8 NB
(Pb-Free)
TSSOP−8
(Pb-Free)
3W MG
G
1
4
MC100EPT26
www.onsemi.com
2
1
2
3
45
6
7
8
Q0
GND
V
CC
Figure 1. 8-Lead Pinout and Logic Diagram
D
Q1D
V
BB
NC
LVTTL
LVPECL
(Top View)
Table 1. PIN DESCRIPTION
Pin Function
Q0, Q1 LVTTL Outputs
D0**, D1** Differential LVPECL Inputs Pair
V
CC
Positive Supply
V
BB
Output Reference Voltage
GND Ground
NC No Connect
EP (DFN8 only) Thermal exposed pad must be con-
nected to a sufficient thermal conduit. Electric-
ally connect to the most negative supply (GND)
or leave unconnected, floating open.
** Pins will default to V
CC
/2 when left open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
50 kW
Internal Input Pullup Resistor
50 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC−8 NB
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 117 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100EPT26
www.onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V 3.8 V
V
IN
Input Voltage GND = 0 V V
I
≤ V
CC
0 to 3.8 V
I
BB
V
BB
Sink/Source ±0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
SOIC−8 NB
190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
T
sol
Wave Solder (Pb-Free) 265 °C
q
JC
Thermal Resistance (Junction-to-Case) (Note 1) DFN8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. PECL INPUT DC CHARACTERISTICS (V
CC
= 3.3 V; GND = 0.0 V (Note 1))
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
V
IH
Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV
V
IL
Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV
V
BB
Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 2)
1.2 3.3 1.2 3.3 1.2 3.3 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current
D
D
−150
−150
−150
−150
−150
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input parameters vary 1:1 with V
CC
.
2. V
IHCMR
min varies 1:1 with GND, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the
differential input signal.
P1-P3P4-P6P7-P8

MC100EPT26DTR2G

Mfr. #:
Buy MC100EPT26DTR2G
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels 1:2 Fanout Diff LVPECL to LVTTL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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