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FM16W08-SG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
FM16W08
64-Kbit (8 K × 8) Wide Voltage Bytewide
F-RAM Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-86210 Rev. *F Revised September 8, 2015
64-Kbit (8 K × 8) Wide Voltage Bytewide F-RAM Memory
Features
■ 64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8 K × 8
❐ High-endurance 100 trillion (10
14
) read/writes
❐ 151-year data retention (see the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ SRAM and EEPROM compatible
❐ Industry-standard 8 K × 8 SRAM and EEPROM pinout
❐ 70-ns access time, 130-ns cycle time
■ Superior to battery-backed SRAM modules
❐ No battery concerns
❐ Monolithic reliability
❐ True surface mount solution, no rework steps
❐ Superior for moisture, shock, and vibration
❐ Resistant to negative voltage undershoots
■ Low power consumption
❐ Active current 12 mA (max)
❐ Standby current 20 A (typ)
■ Wide voltage operation: V
DD
= 2.7 V to 5.5 V
■ Industrial temperature: –40 C to +85 C
■ 28-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM16W08 is a 8 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM16W08 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Minimum read and write cycle times
are equal. The F-RAM memory is nonvolatile due to its unique
ferroelectric memory process. These features make the
FM16W08 ideal for nonvolatile memory applications requiring
frequent or rapid writes.
The device is available in a 28-pin SOIC surface mount package.
Device specifications are guaranteed over the industrial
temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
Logic Block Diagram
Address Latch and Decoder
CE
Control
Logic
WE
A
I/O Latch & Bus Driver
OE
DQ
8 K x 8
F-RAM Array
12-0
7-0
A
12-0
FM16W08
Document Number: 001-86210 Rev. *F Page 2 of 18
Contents
Pinout ................................................................................3
Pin Definitions ..................................................................3
Device Operation ..............................................................4
Memory Architecture ...................................................4
Memory Operation .......................................................4
Read Operation ...........................................................4
Write Operation ........................................................... 4
Pre-charge Operation ..................................................4
Endurance .........................................................................4
F-RAM Design Considerations ........................................5
Maximum Ratings .............................................................7
Operating Range ...............................................................7
DC Electrical Characteristics ..........................................7
Data Retention and Endurance .......................................7
Capacitance ......................................................................8
Thermal Resistance ..........................................................8
AC Test Conditions ..........................................................8
AC Switching Characteristics .........................................9
SRAM Read Cycle ......................................................9
SRAM Write Cycle ..................................................... 10
Power Cycle Timing .......................................................12
Functional Truth Table ...................................................13
Ordering Information ......................................................14
Ordering Code Definitions ......................................... 14
Package Diagram ............................................................15
Acronyms ........................................................................16
Document Conventions .................................................16
Units of Measure ....................................................... 16
Document History Page .................................................17
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
FM16W08
Document Number: 001-86210 Rev. *F Page 3 of 18
Pinout
Figure 1. 28-pin SOIC pinout
Pin Definitions
Pin Name I/O Type Description
A
12
–A
0
Input Address inputs: The 13 address lines select one of 8,192 bytes in the F-RAM array.
DQ
7
–DQ
0
Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array.
WE Input Write Enable: A write cycle begins when WE is asserted. Asserting WE LOW causes the FM16W08 to
write the contents of the data bus to the address location latched by the falling edge of CE.
CE
Input Chip Enable: The device is selected when CE is LOW. Asserting CE LOW causes the address to be
latched internally. Address changes that occur after CE goes LOW will be ignored until the next falling
edge occurs.
OE
Input Output Enable: When OE is LOW, the FM16W08 drives the data bus when the valid read data is
available. Deasserting OE
HIGH tristates the DQ pins.
V
SS
Ground Ground for the device. Must be connected to the ground of the system.
V
DD
Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
DQ
4
DQ
5
DQ
6
DQ
7
OE
A
8
NC
WE
A
9
A
10
A
11
V
DD
CE
DQ
3
NC
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
A
12
A
7
A
6
A
5
A
4
28-pin SOIC
(x 8)
Top view
(not to scale)
1
2
3
4
13
14
5
6
7
8
9
10
11
12
16
15
19
18
17
21
20
24
23
22
26
25
28
27
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

FM16W08-SG

Mfr. #:
Buy FM16W08-SG
Manufacturer:
Cypress Semiconductor
Description:
F-RAM 64Kb 70ns 8K x 8 Parallel FRAM
Lifecycle:
New from this manufacturer.
Delivery:
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