Document Number: 001-86210 Rev. *F Page 10 of 18
SRAM Write Cycle
t
WC
t
WC
Write cycle time 145 – 130 – ns
t
CA
– Chip enable active time 80 – 70 – ns
t
CW
t
SCE
Chip enable to write enable HIGH 80 – 70 – ns
t
PC
– Pre-charge time 65 – 60 – ns
t
WP
t
PWE
Write enable pulse width 50 – 40 – ns
t
AS
t
SA
Address setup time 0–0–ns
t
AH
t
HA
Address hold time 15 – 15 – ns
t
DS
t
SD
Data input setup time 40 – 30 – ns
t
DH
t
HD
Data input hold time 0–0–ns
t
WZ
[5, 6]
t
HZWE
Write enable LOW to output HI-Z – 15 – 15 ns
t
WX
[6]
– Write enable HIGH to output driven 10 – 10 – ns
t
HZ
[5]
– Chip enable to output HI-Z – 15 – 15 ns
t
WS
[7]
– Write enable to CE LOW setup time 0 – 0 – ns
t
WH
[7]
– Write enable to CE HIGH hold time 0 – 0 – ns
AC Switching Characteristics (continued)
Over the Operating Range
Parameters
[2]
Description
V
DD
= 2.7 V to 3.0 V V
DD
= 3.0 V to 5.5 V
Unit
Cypress
Parameter
Alt Parameter Min Max Min Max
Notes
5. t
WZ
and t
HZ
is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
6. This parameter is characterized but not 100% tested.
7. The relationship between CE
and WE determines if a CE or WE controlled write occurs.
