FemtoClock
®
NG Crystal-to-HCSL
Clock Generator
841654
DATASHEET
841654 REVISION A 4/20/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 841654 is an optimized PCIe and sRIO clock generator.
The device uses a 25MHz parallel crystal to generate 100MHz
and 125MHz clock signals, replacing solutions requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (< 1ps rms) suitable to clock components requiring precise and
low-jitter PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the 841654 can also drive the
high-speed sRIO and PCIe SerDes clock inputs of communication
processors, DSPs, switches and bridges.
FEATURES
Four differential HCSL clock outputs: confi gurable for PCIe
(100MHz) and sRIO (100MHz or 125MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
Selectable crystal oscillator interface, 25MHz, 18pF parallel reso-
nant crystal or LVCMOS/LVTTL single-ended reference
clock input
Supports the following output frequencies:
100MHz or 125MHz
VCO: 500MHz
PLL bypass and output enable
RMS phase jitter at 100MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
Full 3.3V power supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
841654
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
VDD
REF_OUT
GND
QA0
nQA0
V
DDOA
GND
QA1
nQA1
nREF_OE
BYPASS
REF_IN
REF_SEL
V
DDA
IREF
FSEL0
FSEL1
QB0
nQB0
V
DDOB
GND
QB1
nQB1
MR/nOE
V
DD
XTAL_IN
XTAL_OUT
GND
0
1
1
0
M = ÷20
÷NA
÷NB
OSC
FemtoClock
PLL
VCO = 500MHz
XTAL_IN
XTAL_OUT
REF_IN
REF_SEL
IREF
BYPASS
FSEL[0:1]
MR/nOE
nREF_OE
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
REF_OUT
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841654 DATA SHEET
2 REVISION A 4/20/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1, 18 V
DD
Power Core supply pins.
2 REF_OUT Output
Single-ended reference frequency clock output.
LVCMOS/LVTTL interface levels.
3, 7, 15, 22 GND Power Power supply ground.
4, 5,
8, 9
QA0, nQA0,
QA1, nQA1
Ouput Differential Bank A output pairs. HCSL interface levels.
6V
DDOA
Power Output supply pin for Bank A outputs.
10 nREF_OE Input Pullup
Active low REF_OUT enable/disable. See Table 3E.
LVCMOS/LVTTL interface levels.
11 BYPASS Input Pulldown
Selects PLL operation/PLL bypass operation.
See Table 3C. LVCMOS/LVTTL interface levels.
12 REF_IN Input Pulldown
Single-ended PLL reference clock input.
LVCMOS/LVTTL interface levels.
13 REF_SEL Input Pulldown
Reference select. Selects the input reference source.
See Table 3B. LVCMOS/LVTTL interface levels.
14 V
DDA
Power Analog supply pin.
16, 17
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
19 MR/nOE Input Pulldown
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the differential outputs are in high impedance
(HiZ). When logic LOW, the internal dividers and the differential outputs are
enabled. See Table 3D. LVCMOS/LVTTL interface levels.
20, 21
24, 25
nQB1, QB1
nQB0, QB0
Output Differential Bank B output pairs. HCSL interface levels.
23 V
DDOB
Power Output supply pin for Bank B outputs.
26, 27
FSEL1,
FSEL0
Input Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
28 IREF Output
HCSL current reference external resistor output. A fi xed precision resistor
(RREF = 475Ω) from this pin to ground provides a reference current used
for differential current-mode QA[0:1]/nQA[0:1] and QB[0:1]/nQB[0:1] clock
outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input PullupResistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
REVISION A 4/20/15
841654 DATA SHEET
3 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
TABLE 3B. REF_SEL FUNCTION TABLE
TABLE 3D. MR/nOE FUNCTION TABLE
TABLE 3C. BYPASS FUNCTION TABLE
Input
REF_SEL Input Reference
0 XTAL (default)
1 REF_IN
Input
BYPASS PLL Confi guration
NOTE 1
0 PLL on (default)
1 PLL bypassed (QA, QB = fref/N)
NOTE 1: Asynchronous function.
Input
MR/nOE Function
NOTE 1
0 Outputs enabled (default)
1 Device reset, outputs disabled (High Impedance)
NOTE 1: Asynchronous function.
TABLE 3A. FSELX FUNCTION TABLE (f
ref
= 25MHZ)
TABLE 3E. nREF_OE FUNCTION TABLE
Input
nREF_OE Function
NOTE 1
0 REF_OUT enabled
1 REF_OUT disabled (High Impedance) (default)
NOTE 1: Asynchronous function.
Inputs Outputs Frequency Settings
FSEL1 FSEL0 M QA0:1/nQA0:1 QB0:1/nQB0:1
0 0 20 VCO/5 (100MHz) VCO/5 (100MHz) (default)
0 1 20 VCO/5 (100MHz) VCO/4 (125MHz)
1 0 20 VCO/5 (100MHz) QB0:1 = L, nQB0:1 = H
1 1 20 VCO/4 (125MHz) VCO/4 (125MHz)

841654AGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 4 HCSL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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