MIC2186 Micrel, Inc.
M9999-042205 14 April 2005
Pin
6
Voltage
Amplifier
V
REF
1.245V
MIC2186
R1
R2
Figure 11.
The output voltage is determined by the equation below.
VV 1
R1
R2
O
REF
=×+
Where: Vref for the MIC2186 is nominally 1.245V. Lower
values of resistance are preferred to prevent noise from
apprearing on the Vfb pin. A typically recommended value for
R1 is 10K.
Decoupling Capacitor Selection
The 1uf decoupling capacitor is used to stabilize the internal
regulator and minimize noise on the Vdd pin. Placement of
this capacitor is critical to the proper operation of the MIC2186.
It must be next to the Vdd and signal ground pins and routed
with wide etch. The capacitor should be a good quality
ceramic. Incorrect placement of the Vdd decoupling capaci-
tor will cause jitter and/or oscillations in the switching wave-
form as well as variations in the overcurrent limit.
A minimum 0.1uf ceramic capacitor is required to decouple
the Vin. The capacitor should be placed near the IC and
connected directly between pins 10 (Vcc) and 5 (SGND). A
0.1uf capacitor is required to decouple Vref. It should be
located near the Vref pin.
Efficiency calculation and considerations
Efficiency is the ratio of output power to input power. The
difference is dissipated as heat in the boost converter. The
significant contributors at light output loads are:
* The VinA pin supply current.
* The VinP pin supply current which includes the
current required to switch the external
MOSFETs
* Core losses in the inductor
To maximize efficiency at light loads:
* Use a low gate charge MOSFET or use the
smallest MOSFET, which is still adequate for the
maximum output current.
*Allow the MIC2186 to run in skip mode at lower
currents. If running in PWM mode, set the
MIC2186 to switch at a lower frequency.
* se a ferrite material for the inductor core, which
has less core loss than an MPP or iron power
core.
The significant contributors to power loss at higher output
loads are (in approximate order of magnitude):
* Resistive on-time losses in the MOSFET
* Switching transition losses in the MOSFET
* Inductor resistive losses
* Current sense resistor losses
* Output capacitor resistive losses (due to the
capacitor’s ESR)
To minimize power loss under heavy loads:
* Use Logic level, low on resistance MOSFETs.
Multiplying the gate charge by the on resistance
gives a figure of merit, providing a good balance
between switching and resistive power dissipa-
tion.
* Slow transition times and oscillations on the
voltage and current waveforms dissipate more
power during the turn-on and turn-off of the low
side MOSFET. A clean layout will minimize
parasitic inductance and capacitance in the gate
drive and high current paths. This will allow the
fastest transition times and waveforms without
oscillations. Low gate charge MOSFETs will
switch faster than those with higher gate charge
specifications.
* For the same size inductor, a lower value will
have fewer turns and therefore, lower winding
resistance. However, using too small of a value
will increase the inductor current and therefore
require more output capacitors to filter the output
ripple.
* Lowering the current sense resistor value will
decrease the power dissipated in the resistor.
However, it will also increase the overcurrent
limit and may require larger MOSFETs and
inductor components to handle the higher
currents.
* Use low ESR output capacitors to minimize the
power dissipated in the capacitor’s ESR.
