Technical Note
4/14
BD67929EFV
www.rohm.com
2010.12 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Capacitor for noise to
Hall signal.
Setting range is
0.010.1µF.
Resistor and capacitor
for PLL control.
Capacitor for
compensation of
current feedback roop.
Capacitor to set
the PWM frequency.
Bypass capacitor.
Setting range is
47µF470µF
(electrolytic)
0.01µF0.1µF
(multilayer ceramic etc.)
Resistor to detect the
Motor current.
Setting range is
0.25Ω~1.00Ω.
Resistor to set output
signal level of Hall
element.
Resistor and Capacitor
is to reduce the noise
of CR terminal.
Capacitor for
internal Regulator and
regulator for Hall element.
Capacitor to set the detection time for
protection circuit. Setting range is
0.01µF0.47µF.
CS
VREG
TEST
PROCLK
GND
FG
LD
CL
K
SS
PD
EO
EI
OSC
CNF
HWP
HVP
HUN
HUP
HWN
HVN
U
VCC
HB
RNF
W
V
VCC
0.01µF 100µF
1K
330pF
0.1µF
0.1µF
33pF
10nF
10nF
10nF
0.33
20
17
19
11
13
14
15
10
12
25
27
16
22
3
24
Regulator
5
8
2
6
18
4
TSD
HALL
HYS
COMP
7
21
23
RESET UVLO
OCP OVLO PRO_OSC
LOGIC
PWM
1
9
HALL
BIAS
SB
BRMODE
28
26
Pin function
Pin No Pin name Function Pin No Pin name Function
1 GND Ground 15 HUP Hall signal input terminal
2 VCC Power supply terminal 16 VREG 5V regulator output terminal
3 FG FG output terminal 17 PD Phase comparison output terminal
4 CS
Current detection comparator
input terminal
18 TEST Testing terminal
5 RNF
Connection terminal of resistor
for output current detection
19 EI Error amplifier input terminal
6 W Output terminal 20 EO Error amplifier output terminal
7 V Output terminal 21 PROCLK
Connection terminal of a capacitor
to set the clock cycle for protection
8 U Output terminal 22 CLK Speed control clock input terminal
9 HB Bias terminal for Hall element 23 SS Start/stop signal input terminal
10 HWN Hall signal input terminal 24 LD
Phase locked detection
output terminal
11 HWP Hall signal input terminal 25 OSC
Connection terminal of capacitor
to set PWM oscillating frequency
12 HVN Hall signal input terminal 26 BRMODE
Switch terminal of deceleration
mode in servo
13 HVP Hall signal input terminal 27 CNF
Connection terminal of
capacitor for current sense amp
14 HUN Hall signal input terminal 28 SB Short brake signal input terminal
Block diagram & Application circuit diagram
Block diagram & Application circuit diagram
Technical Note
5/14
BD67929EFV
www.rohm.com
2010.12 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Terminal function
HWP, HVP, HUP, HWN, HVN, HUN/Hall signal input terminal
These terminals are the input terminals of the output signals from Hall elements. This has the comparator with hysteresis.
The width of hysteresis voltage is ±12mV(Typ.). The output of this comparator will be high if the voltage of HxP terminal
is greater than the voltage of HxN terminal by 12mV, and the level will be low if the voltage of HxP terminal is less than
the voltage of HxN terminal by 12mV. For the countermeasures against noise interface with Hall inputs, the connection of
a capacitor with a capacitance of approximately 0.01 - 0.1µF between HxP terminal and HxN terminal.
PD/Phase comparison output terminal
This terminal outputs the signal that is the comparison of FG signal and CLK signal.
EI/Error amplifier input terminal
This terminal is the input terminal of the error amplifier.
EO/Error amplifier output terminal
This terminal is the output terminal of the error amplifier. It is connected to the input terminal of motor torque command
signal inside the IC.
CLK/Speed control clock input terminal
This terminal is the CLK signal input terminal to control the speed. This terminal has the 100kΩ resistor which is
pulled-up to the internal regulator. This block detect the falling edge. In case that there is the noise on the CLK signal, it
makes the miscount of the CLK signal. Be sure to design the pattern without the influence of the noise.
SS/Start/Stop signal input terminal
This terminal makes the motor start or stop.
This terminal has the 100kΩ resistor which is pulled-up to the internal regulator.
SS
LO start
HI stop
When SS=HI, IC becomes stop condition. Stop condition is Free Run or Short Brake that decided by SB terminal.
Moreover, it makes the HB terminal off, and shut down the current to the Hall element. It is very useful to low power
consumption.
LD/Phase locked detection output terminal
When the rotation count of the motor is within 10% of the target rotation count, the LD terminal becomes LO.
This terminal is open drain type output, please connect to the external regulator (05.5V recommended) through the
resistor. The capability of this terminal is 15mA maximum, please set the voltage of the external regulator and the value of
resistor to be within 15mA.
OSC/Connection terminal of capacitor to set PWM oscillating frequency
This terminal is the connection terminal of capacitor to make the triangle waveform that set the PWM frequency.
f
PWM
= 44µ / C [Hz]
ex.) when C=220pF, f=200kHz
CNF/Connection terminal of capacitor of Current Sense Amp.
This terminal is the connection terminal of capacitor to compensate the phase of CS Amplifier.
SB/Short brake signal input terminal
This terminal is the input signal terminal that set output condition when the voltage of SS is HI. This terminal has the
100kΩ resistor which is pulled-up to the internal regulator. When the voltage of SB terminal turns to LO, all low side
MOS FET turns to ON, and it should be short brake condition. It is very useful to reduce the speed quickly.
SB stop mode
LO Short brake mode
HI Free run mode
BRMODE/PLL brake setting terminal
This IC has the two kinds of deceleration method. The method is configurable by which terminal to connect with
BRMODE, VREG or GND terminal. This terminal has the 100kΩ resistor which is pulled-up to the internal regulator.
BRMODE deceleration method
GND short brake
VREG free run
Technical Note
6/14
BD67929EFV
www.rohm.com
2010.12 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
VREG/5V regulator output terminal
This terminal is the connection terminal of capacitor to stabilize the 5V output of internal regulator. It should be connected
with the capacitor (0.01µF-1µF) to the ground. This terminal is used as the regulator to the Hall element too. The road
current should be within 20mA.
PROCLK/Connection terminal of a capacitor to set the clock cycle for protection
This terminal is the connection terminal of capacitor to set the time of detection.
The period of PROCLK=C×200k[s]
ex.) when C=0.1µF, The period of PROCLK=20m[s]
HB/Bias terminal for Hall element
This terminal is the open collector type, and low side switch. By connecting the GND side of Hall element to the HB, the
bias current of the Hall element will be turned off with the SS set to high or open. It is very useful for the low power
consumption because the bias current for Hall element will be 0µA.
FG/FG output terminal
This terminal outputs the signal which indicate the rotation count, which is synthesize from Hall signal of U-phase.
This terminal is open drain type output, it should be pulled-up to the external regulator (0-5.5V) through the resistor.
The capability of FG terminal is 15mA maximum, please set the voltage of external regulator and the value of resistor to
be within 15mA.
CS/Current detection comparator input terminal
In this IC, CS terminal, which is the input terminal of current limit comparator, is independently arranged in order to
decrease the lowering of current-detecting accuracy caused by the wire impedance inside the IC of RNF terminal.
Therefore, please be sure to connect RNF terminal and CS terminal together when using in the case of PWM constant
current control. In addition, because the wires from CS terminal is connected near the current-detecting resistor in the
case of interconnection, the lowering of current-detecting accuracy, which is caused by the impedance of board pattern
between RNF terminal and the current-detecting resistor, can be decreased. Moreover, please design the pattern in such
a way that there is no noise plunging. In addition, please be careful because if terminal of RNF is shorted to GND, large
current flows without normal PWM constant current control and, then there is danger that OCP or TSD will operate.
To reduce the PWM noise influence, please out the filter between RNF terminal and CS terminal.
The cut-off frequency is below
f = 1 / (2π×R1×C1)
ex.) when C1=330pF, R1=1kHz f=483[kHz]
U, V, W/Output terminal
Motor's drive current is flowing in it, so please wires in such a way that the wire is thick & short has low impedance. It is
also effective to add a Shot-key diode if output has positive or negative great fluctuation when large current is used etc.,
for example, if counter electromotive voltage etc. is great. Moreover, in the output terminal, there is built-in clamp
component for preventing of electrostatic destruction. If steep pulse or voltage of surge more that maximum absolute
rating is applied, this clamp component operates, as a result there is the danger of even destruction, so please be sure
that the maximum absolute rating must not be exceeded.
Hall signal
FG
HUN
HUP
CS R1 RNF
C1 R
RNF

BD67929EFV-E2

Mfr. #:
Manufacturer:
Description:
Motor / Motion / Ignition Controllers & Drivers NPN+NPN Driver Transistor
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