MAX5104CEE+T

MAX5104
Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface
_______________________________________________________________________________________ 7
allowing the MAX5104 to recall the output state prior to
entering power-down when returning to normal mode.
Exit power-down by recalling the previous condition or
by updating the DAC with new information. When
returning to normal operation (exiting power-down),
wait 20µs for output stabilization.
Serial Interface
The MAX5104’s 3-wire serial interface is compatible
with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3)
serial-interface standards. The 16-bit serial input word
consists of 1 address bit, 2 control bits, 12 bits of data
(MSB to LSB), and 1 sub-bit as shown in Figure 4. The
address and control bits determine the MAX5104’s
response, as outlined in Table 1.
FUNCTION
A0 C1 C0
D11.......................D0
(MSB) (LSB)
0 0 1 12-bit DAC data Load input register A; DAC registers are unchanged.
0 1 1 12-bit DAC data
Load all DAC registers from the shift register
(start up both DACs with new data).
1 1 0 12-bit DAC data Load input register B; all DAC registers are updated.
0 1 0 12-bit DAC data Load input register A; all DAC registers are updated.
1 0 1 12-bit DAC data Load input register B; DAC registers are unchanged.
0 0 0 1 1 0 X XXXXXXXX
Power Down DAC A (provided PDL = 1).
0 0 0 1 0 1 X XXXXXXXX
Update DAC register B from input register B
(start up DAC B with data previously stored in input register B).
0 0 0 0 0 1 X XXXXXXXX
Update DAC register A from input register A
(start up DAC A with data previously stored in input register A).
1 1 1 XXXXXXXXXXXX
Shut down both DACs (provided PDL = 1).
1 0 0 XXXXXXXXXXXX
Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input registers).
0 0 0 1 1 1 X XXXXXXXX
Power Down DAC B (provided PDL = 1).
0 0 0 0 1 0 X XXXXXXXX UPO goes low (default).
0 0 0 0 1 1 X XXXXXXXX UPO goes high.
0 0 0 1 0 0 1 XXXXXXXX Mode 1, DOUT clocked out on SCLK’s rising edge.
0 0 0 1 0 0 0 XXXXXXXX Mode 0, DOUT clocked out on SCLK’s falling edge (default).
0 0 0 0 0 0 X XXXXXXXX No operation (NOP).
Table 1. Serial-Interface Programming Commands
X = Don’t care
Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub-bit, always zero.
SCLK
DIN
CS
SK
SO
I/O
MICROWIRE
PORT
MAX5104
Figure 2. Connections for MICROWIRE
16-BIT SERIAL WORD
S0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAX5104
Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface
8 _______________________________________________________________________________________
The MAX5104’s digital inputs are double buffered,
which allows any of the following: loading the input reg-
ister(s) without updating the DAC register(s), updating
the DAC register(s) from the input register(s), or updating
the input and DAC registers concurrently. The address
and control bits allow the DACs to act independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, MICROWIRE), with CS low during
this period. The address and control bits determine
which register will be updated, and the state of the reg-
isters when exiting power-down. The 3-bit address/con-
trol determines the following:
• Registers to be updated
• Clock edge on which data is to be clocked out via the
serial-data output (DOUT)
• State of the user-programmable logic output
• Configuration of the device after power-down
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data; otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the address and control bits. The maximum
clock frequency guaranteed for proper operation is
10MHz. Figure 6 shows a more detailed timing diagram
of the serial interface.
DIN
SCLK
CS
MOSI
SCK
I/O
SPI/QSPI
PORT
SS
+5V
CPOL = 0, CPHA = 0
MAX5104
Figure 3. Connections for SPI/QSPI
Figure 5. Serial-Interface Timing Diagram
SCLK
DIN
CS
COMMAND
EXECUTED
9
8
16
1
C1
A0 S0
C0
D11
D10
D9
D8 D5 D4 D3 D2 D1 D0D7 D6
Figure 4. Serial-Data Format
1 Address/2 Control Bits
A0
Address Bits
C1, C0
Control Bits
12 Data Bits
D11.......................D0
MSB...Data Bits...LSB
0
S0
Sub
Bit
16 Bits of Serial Data
MSB...................................................................................LSB
MAX5104
Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface
_______________________________________________________________________________________ 9
SCLK
DIN
t
CSO
t
CSS
t
CL
t
CH
t
CP
t
CSW
t
CS1
t
CSH
t
DS
t
DH
CS
Figure 6. Detailed Serial-Interface Timing Diagram
TO OTHER
SERIAL DEVICES
MAX5104
DIN
SCLK
CS
MAX5104 MAX5104
DINDOUT DOUT DOUT
SCLK
DIN
SCLK
CS
CS
TO OTHER
SERIAL DEVICES
MAX5104
DIN
SCLK
MAX5104
DIN
SCLK
MAX5104
DIN
SCLK
DIN
SCLK
CS1
CS2
CS3
CS
CS
CS
Figure 7. Daisy Chaining MAX5104s
Figure 8. Multiple MAX5104s Sharing a Common DIN Line

MAX5104CEE+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 2Ch Precision DAC
Lifecycle:
New from this manufacturer.
Delivery:
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