AD9883AKSTZ-RL110 Datasheet AD9883AKSTZ-140, AD9883AKSTZ-110, AD9883ABSTZ-140 | P16-P18

REV. B

AD9883A

–15–

Table VI. Control Register Map

Write and

Hex Read or Default Register

Address Read Only Bits Value Name Function

00H RO 7:0 Chip Revision An 8-bit register that represents the silicon revision level.

Revision 0 = 0000 0000.

01H* R/W 7:0 01101001 PLL Div MSB This register is for Bits [11:4] of the PLL divider. Greater values mean

the PLL operates at a faster rate. This register should be loaded first

whenever a change is needed. This will give the PLL more time to lock.

02H* R/W 7:4 1101**** PLL Div LSB Bits [7:4] of this word are written to the LSBs [3:0] of the

PLL divider word.

03H R/W 7:3 01****** Bits [7:6] VCO Range. Selects VCO frequency range.

(See PLL description.)

**001*** Bits [5:3] Charge Pump Current. Varies the current that drives the

low-pass filter. (See PLL description.)

04H R/W 7:3 10000*** Phase Adjust ADC Clock Phase Adjustment. Larger values mean more delay.

(1 LSB = T/32)

05H R/W 7:0 10000000 Clamp Places the Clamp signal an integer number of clock periods after the trail-

Placement ing edge of the Hsync signal.

06H R/W 7:0 10000000 Clamp Number of clock periods that the Clamp signal is actively clamping.

Duration

07H R/W 7:0 00100000 Hsync Output Sets the number of pixel clocks that HSOUT will remain active.

Pulsewidth

08H R/W 7:0 10000000 Red Gain Controls ADC input range (contrast) of each respective channel.

Greater values give less contrast.

09H R/W 7:0 10000000 Green Gain

0AH R/W 7:0 10000000 Blue Gain

0BH R/W 7:1 1000000

Red Offset Controls dc offset (brightness) of each respective channel. Greater

values decrease brightness.

0CH R/W 7:1 1000000

Green Offset

0DH R/W 7:1 1000000

Blue Offset

0EH R/W 7:0 0******* Sync Control Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by

chip, Logic 1 = Polarity set by Bit 6 in register 0EH.)

*1****** Bit 6 – Hsync Input Polarity. Indicates polarity of incoming Hsync

signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)

**0***** Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync,

Logic 1 = Logic Low Sync.)

***0**** Bit 4 – Active Hsync Override. If set to Logic 1, the user can select

the Hsync to be used via Bit 3. If set to Logic 0, the active interface

is selected via Bit 6 in register 14H.

****0*** Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active

sync. Logic 1 selects Sync-on-Green as the active sync. Note that the

indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both

syncs are active. (Bits 1, 7 = Logic 1 in register 14H.)

*****0** Bit 2 – Vsync Output Invert. (Logic 1 = No Invert, Logic 0 = Invert.)

******0* Bit 1 – Active Vsync Override. If set to Logic 1, the user can select

the Vsync to be used via Bit 0. If set to Logic 0, the active interface

is selected via Bit 3 in register 14H.

*******0 Bit 0 – Active Vsync Select. Logic 0 selects Raw Vsync as the output

Vsync. Logic 1 selects Sync Separated Vsync as the output Vsync.

Note that the indicated

Vsync will be used only if Bit 1 is set to Logic 1.

2-Wire Serial Register Map

The AD9883A is initialized and controlled by a set of registers,

which determine the operating modes. An external controller is

employed to write and read the control registers through the

two-line serial interface port.

REV. B

AD9883A

–16–

Table VI. Control Register Map (continued)

Write and

Hex Read or Default Register

Address Read Only Bits Value Name Function

0FH R/W 7:1 0******* Bit 7 – Clamp Function. Chooses between Hsync for Clamp

signal or another external signal to be used for clamping.

(Logic 0 = Hsync, Logic 1 = Clamp.)

*1****** Bit 6 – Clamp Polarity. Valid only with external Clamp signal.

(Logic 0 = Active High, Logic 1 Selects Active Low.)

**0***** Bit 5 – Coast Select. Logic 0 selects the coast input pins to be

used for the PLL coast. Logic 1 selects Vsync to be used for the

PLL coast.

***0**** Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by

chip, Logic 1 = Polarity set by Bit 3 in register 0FH.)

****1*** Bit 3 – Coast Polarity. Selects polarity of external Coast signal.

(Logic 0 = Active Low, Logic 1 = Active High.)

*****1** Bit 2 – Seek Mode Override. (Logic 1 = Allow Low Power Mode,

Logic 0 = Disallow Low Power Mode.)

******1* Bit 1 – PWRDN. Full Chip Power-Down, Active Low. (Logic 0 =

Full Chip Power-Down, Logic 1 = Normal.)

10H R/W 7:3 10111*** Sync-on-Green Sync-on-Green Threshold. Sets the voltage level of the Sync-on-

Threshold Green slicer’s comparator.

*****0** Bit 2 – Red Clamp Select. Logic 0 selects clamp to ground.

Logic 1 selects clamp to midscale (voltage at Pin 37).

******0* Bit 1 – Green Clamp Select. Logic 0 selects clamp to ground.

Logic 1 selects clamp to midscale (voltage at Pin 37).

*******0 Bit 0 – Blue Clamp Select. Logic 0 selects clamp to ground.

Logic 1 selects clamp to midscale (voltage at Pin 37).

11H R/W 7:0 00100000 Sync Separator Sync Separator Threshold. Sets how many internal 5 MHz clock

Threshold periods the sync separator will count to before toggling high or low.

This should be set to some number greater than the maximum

Hsync or equalization pulsewidth.

12H R/W 7:0 00000000 Pre-Coast Pre-Coast. Sets the number of Hsync periods that Coast becomes

active prior to Vsync.

13H R/W 7:0 00000000 Post-Coast Post-Coast. Sets the number of Hsync periods that Coast stays

active following Vsync.

14H RO 7:0 Sync Detect Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the

analog interface; otherwise it is set to Logic 0.

Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync

is being used. (Logic 0 = Hsync Input Pin, Logic 1 = Hsync from

Sync-on-Green.)

Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low,

Logic 1 = Active High.)

Bit 4 – Vsync Detect. It is set to Logic 1 if Vsync is present on the

analog interface; otherwise it is set to Logic 0.

Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync

is being used. (Logic 0 = Vsync Input Pin, Logic 1 = Vsync from

Sync Separator.)

Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low,

Logic 1 = Active High.)

Bit 1 – Sync-on-Green Detect. It is set to Logic 1 if sync is present

on the Green video input; otherwise it is set to 0.

Bit 0 – Input Coast Polarity Detect. (Logic 0 = Active Low, Logic 1 =

Active High.)

15H R/W 7:0 1111**** Test Register Bits [7:4] Reserved for future use.

****1*** Bit 3 – Must be set to 1 for proper operation.

*****1** Bit 2 – Must be set to 1 for proper operation.

******1* Bit 1 – 4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, Logic 1=

4:4:4 mode)

*******1 Bit 0 – Must be set to 0 for proper operation.

REV. B

AD9883A

–17–

2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP

IDENTIFICATION

00 7–0 Chip Revision

An 8-bit register that represents the silicon revision. Revi-

sion 0 = 0000 0000, Revision 1 = 0000 0001, Revision 2 =

0000 0010.

PLL DIVIDER CONTROL

01 7–0 PLL Divide Ratio MSBs

The 8 most significant bits of the 12-bit PLL divide ratio

PLLDIV. (The operational divide ratio is PLLDIV + 1.)

The PLL derives a master clock from an incoming Hsync

signal. The master clock frequency is then divided by an

integer value, such that the output is phase-locked to

Hsync. This PLLDIV value determines the number of

pixel times (pixels plus horizontal blanking overhead) per

line. This is typically 20% to 30% more than the number

of active pixels in the display.

The 12-bit value of the PLL divider supports divide ratios

from 2 to 4095. The higher the value loaded in this regis-

ter, the higher the resulting clock frequency with respect

to a fixed Hsync frequency.

VESA has established some standard timing specifications

that assist in determining the value for PLLDIV as a

function of horizontal and vertical display resolution and

frame rate (Table V).

However, many computer systems do not conform pre-

cisely to the recommendations, and these numbers should

be used only as a guide. The display system manufacturer

should provide automatic or manual means for optimizing

PLLDIV. An incorrectly set PLLDIV will usually produce

one or more vertical noise bars on the display. The greater

the error, the greater the number of bars produced.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 69H, PLLDIVL = DxH).

The AD9883A updates the full divide ratio only when the

LSBs are changed. Writing to the MSB by itself will not

trigger an update.

02 7–4 PLL Divide Ratio LSBs

The 4 least significant bits of the 12-bit PLL divide ratio

PLLDIV. The operational divide ratio is PLLDIV + 1.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 69H, PLLDIVL = DxH).

The AD9883A updates the full divide ratio only when this

CLOCK GENERATOR CONTROL

03 7–6 VCO Range Select

Two bits that establish the operating range of the clock

generator.

VCORNGE must be set to correspond with the desired

operating frequency (incoming pixel rate).

The PLL gives the best jitter performance at high fre-

quencies. For this reason, to output low pixel rates and

still get good jitter performance, the PLL actually operates

at a higher frequency but then divides down the clock rate

afterwards. Table VII shows the pixel rates for each VCO

range setting. The PLL output divisor is automatically

selected with the VCO range setting.

Table VII. VCO Ranges

VCORNGE Pixel Rate Range

00 12–32

01 32–64

10 64–110

11 110–140

The power-up default value is 01.

03 5–3 CURRENT Charge Pump Current

Three bits that establish the current driving the loop filter

in the clock generator.

Table VIII. Charge Pump Currents

CURRENT Current (␮A)

000 50

001 100

010 150

011 250

100 350

101 500

110 750

111 1500

CURRENT must be set to correspond with the desired

operating frequency (incoming pixel rate).

The power-up default value is current = 001.

Table VI. Control Register Map (continued)

Write and

Hex Read or Default Register

Address Read Only Bits Value Name Function

16H R/W 7:0 Test Register Reserved for future use.

17H RO 7:0 Test Register Reserved for future use.

18H RO 7:0 Test Register Reserved for future use.

*The AD9883A only updates the PLL divide ratio when the LSBs are written to (register 02H).

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AD9883AKSTZ-RL110

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IC INTERFACE FLAT 110MHZ 80LQFP

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AD9883AKSTZ-RL110

AD9883AKSTZ-RL110

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