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AD9883AKSTZ-RL110

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
REV. B
AD9883A
–18–
04 7–3 Clock Phase Adjust
A 5-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25° shift
in sampling phase.
The power-up default value is 16.
CLAMP TIMING
05 7–0 Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp.
When Clamp Function (Register 0FH, Bit 7) = 0, a clamp
signal is generated internally, at a position established by
the clamp placement and for a duration set by the clamp
duration. Clamping is started (Clamp Placement) pixel
periods after the trailing edge of Hsync. The clamp placement
may be programmed to any value between 1 and 255.
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
When Clamp Function = 1, this register is ignored.
06 7–0 Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
For the best results, the clamp duration should be set to
include the majority of the black reference signal time that
follows the Hsync signal trailing edge. Insufficient clamping
time can produce brightness changes at the top of the screen,
and a slow recovery from large changes in the average picture
level (APL), or brightness.
When Clamp Function = 1, this register is ignored.
Hsync PULSEWIDTH
07 7–0 Hsync Output Pulsewidth
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by the
internally generated, phase-adjusted PLL feedback clock.
The AD9883A then counts a number of pixel clocks equal
to the value in this register. This triggers the trailing edge
of the Hsync output, which is also phase adjusted.
INPUT GAIN
08 7–0 Red Channel Gain Adjust
An 8-bit word that sets the gain of the Red channel.
The AD9883A can accommodate input signals with a
full-scale range of between 0.5 V and 1.0 V p-p. Setting
REDGAIN to 255 corresponds to a 1.0 V input range.
A REDGAIN of 0 establishes a 0.5 V input range. Note
that increasing REDGAIN results in the picture having less
contrast (the input signal uses fewer of the available
converter codes). See Figure 2.
09 7–0 Green Channel Gain Adjust
An 8-bit word that sets the gain of the Green channel. See
REDGAIN (08).
0A 7–0 Blue Channel Gain Adjust
An 8-bit word that sets the gain of the Blue channel. See
REDGAIN (08).
INPUT OFFSET
0B 7–1 Red Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the Red
channel. One LSB of offset adjustment equals approximately
one LSB change in the ADC offset. Therefore, the absolute
magnitude of the offset adjustment scales as the gain of the
channel is changed. A nominal setting of 63 results in the
channel nominally clamping the back porch (during the
clamping interval) to Code 00. An offset setting of 127 results
in the channel clamping to Code 64 of the ADC. An offset
setting of 0 clamps to Code –63 (off the bottom of the
range). Increasing the value of Red Offset decreases the
brightness of the channel.
0C 7–1 Green Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
Green channel. See REDOFST (0B).
0D 7–1 Blue Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
Green channel. See REDOFST (0B).
MODE CONTROL 1
0E 7 Hsync Input Polarity Override
This register is used to override the internal circuitry
that determines the polarity of the Hsync signal going
into the PLL.
Table IX. Hsync Input Polarity Override Settings
Override Bit Function
0Hsync Polarity Determined by Chip
1Hsync Polarity Determined by User
The default for Hsync polarity override is 0 (polarity
determined by chip).
0E 6 HSPOL Hsync Input Polarity
A bit that must be set to indicate the polarity of the
Hsync signal that is applied to the PLL Hsync input.
Table X. Hsync Input Polarity Settings
HSPOL Function
0Active Low
1Active High
Active Low means the leading edge of the Hsync pulse
is negative going. All timing is based on the leading edge
of Hsync, which is the falling edge. The rising edge has no
effect.
Active high is inverted from the traditional Hsync, with
a positive-going pulse. This means that timing will be
based on the leading edge of Hsync, which is now the
rising edge.
The device will operate if this bit is set incorrectly, but the
internally generated clamp position, as established by
Clamp Placement (Register 05H), will not be placed as
expected, which may generate clamping errors.
The power-up default value is HSPOL = 1.
REV. B
AD9883A
–19–
0E 5 Hsync Output Polarity
This bit determines the polarity of the Hsync output and
the SOG output. Table XI shows the effect of this option.
SYNC indicates the logic state of the sync pulse.
Table XI. Hsync Output Polarity Settings
Setting SYNC
0Logic 1 (Positive Polarity)
1Logic 0 (Negative Polarity)
The default setting for this register is 0.
0E 4 Active Hsync Override
This bit is used to override the automatic Hsync selection,
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
Table XII. Active Hsync Override Settings
Override Result
0Autodetermines the Active Interface
1 Override, Bit 3 Determines the Active Interface
The default for this register is 0.
0E 3 Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 4). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
Table XIII. Active HSYNC Select Settings
Select Result
0HSYNC Input
1 Sync-on-Green Input
The default for this register is 0.
0E 2 Vsync Output Invert
This bit inverts the polarity of the Vsync output. Table
XIV shows the effect of this option.
Table XIV. Vsync Output Invert Settings
Setting Vsync Output
0 Invert
1No Invert
The default setting for this register is 0.
0E 1 Active Vsync Override
This bit is used to override the automatic Vsync selection.
To override, set this bit to Logic 1. When overriding, the
active interface is set via Bit 0 in this register.
Table XV. Active Vsync Override Settings
Override Result
0Autodetermine the Active Vsync
1 Override, Bit 0 Determines the Active Vsync
The default for this register is 0.
0E 0 Active Vsync Select
This bit is used to select the active Vsync when the over-
ride bit is set (Bit 1).
Table XVI. Active Vsync Select Settings
Select Result
0Vsync Input
1Sync Separator Output
The default for this register is 0.
0F 7 Clamp Input Signal Source
This bit determines the source of clamp timing.
Table XVII. Clamp Input Signal Source Settings
Clamp Function Function
0Internally Generated Clamp Signal
1 Externally Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the leading edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is active.
The polarity of CLAMP is determined by the Clamp
Polarity bit (Register 0FH, Bit 6).
The power-up default value is Clamp Function = 0.
0F 6 Clamp Input Signal Polarity
This bit determines the polarity of the externally provided
CLAMP signal.
Table XVIII. Clamp Input Signal Polarity Settings
Clamp Function Function
1Active Low
0Active High
A Logic 1 means that the circuit will clamp when CLAMP is
low, and it will pass the signal to the ADC when CLAMP is
high.
A Logic 0 means that the circuit will clamp when CLAMP
is high, and it will pass the signal to the ADC when
CLAMP is low.
The power-up default value is Clamp Polarity = 1.
0F 5 Coast Select
This bit is used to select the active Coast source. The
choices are the Coast Input Pin or Vsync. If Vsync is se-
lected the additional decision of using the Vsync input
pin or the output from the sync separator needs to be
made (Register 0E, Bits 1, 0).
Table XIX. Power-Down Settings
Select Result
0Coast Input Pin
1Vsync (See above Text)
REV. B
AD9883A
–20–
0F 4 Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the Coast signal going into the PLL.
Table XX. Coast Input Polarity Override Settings
Override Bit Result
0Determined by Chip
1Determined by User
The default for coast polarity override is 0.
0F 3 Coast Input Polarity
This bit indicates the polarity of the Coast signal that is
applied to the PLL COAST input.
Table XXI. Coast Input Polarity Settings
Coast Polarity Function
0Active Low
1Active High
Active Low means that the clock generator will ignore
Hsync inputs when Coast is low, and continue operating at
the same nominal frequency until Coast goes high.
Active High means that the clock generator will ignore
Hsync inputs when Coast is high, and continue operating at
the same nominal frequency until Coast goes low.
This function needs to be used along with the Coast
Polarity Override bit (Bit 4).
The power-up default value is 1.
0F 2 Seek Mode Override
This bit is used to either allow or disallow the low power
mode. The low power mode (Seek Mode) occurs when
there are no signals on any of the Sync inputs.
Table XXII. Seek Mode Override Settings
Select Result
1Allow Seek Mode
0Disallow Seek Mode
The default for this register is 1.
0F 1 PWRDN
This bit is used to put the chip in full power-down. See
Power Management Section for details of which blocks
are powered down.
Table XXIII. Power-Down Settings
Select Result
0 Power-Down
1Normal Operation
The default for this register is 1.
10 7-3 Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the Sync-
on-Green slicer to be adjusted. This register adjusts it in
steps of 10 mV, with the minimum setting equaling 10 mV
(11111) and the maximum setting equaling 330 mV (00000).
The default setting is 23, which corresponds to a threshold
value of 100 mV; for a threshold of 150 mV, the setting
should be 18.
10 2 Red Clamp Select
This bit determines whether the Red channel is clamped to
ground or to midscale. For RGB video, all three chan-
nels are referenced to ground. For YCbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 37.
Table XXIV. Red Clamp Select Settings
Clamp Function
0Clamp to Ground
1Clamp to Midscale (Pin 37)
The default setting for this register is 0.
10 1 Green Clamp Select
This bit determines whether the Green channel is clamped
to ground or to midscale.
Table XXV. Green Clamp Select Settings
Clamp Function
0Clamp to Ground
1Clamp to Midscale (Pin 37)
The default setting for this register is 0.
10 0 Blue Clamp Select
This bit determines whether the Blue channel is clamped
to ground or to midscale.
Table XXVI. Blue Clamp Select Settings
Clamp Function
0Clamp to Ground
1Clamp to Midscale (Pin 37)
The default setting for this register is 0.
11 7–0 Sync Separator Threshold
This register is used to set the responsiveness of the sync
separator. It sets how many internal 5 MHz clock periods
the sync separator must count to before toggling high or
low. It works like a low-pass filter to ignore Hsync pulses
in order to extract the Vsync signal. This register should
be set to some number greater than the maximum Hsync
pulsewidth. Note that the sync separator threshold uses an
internal dedicated clock with a frequency of approxi-
mately 5 MHz.
The default for this register is 32.
12 7–0 Pre-Coast
This register allows the coast signal to be applied prior to
the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
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AD9883AKSTZ-RL110

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Buy AD9883AKSTZ-RL110
Manufacturer:
Analog Devices Inc.
Description:
IC INTERFACE FLAT 110MHZ 80LQFP
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