AD73311LARUZ Datasheet AD73311LARSZ-REEL7, AD73311LARSZ, AD73311LARUZ | P22-P24

AD73311

–21–

REV. B

Cascade Operation

The AD73311 has been designed to support up to eight codecs

in a cascade connected to a single serial port, see Figure 31.

The SPORT interface protocol has been designed so that device

addressing is built into the packet of information sent to the

device. This allows the cascade to be formed with no extra hard-

ware overhead for control signals or addressing. A cascade can

be formed in either of the two modes previously discussed.

There may be some restrictions in cascade operation due to the

number of devices configured in the cascade and the serial clock

rate chosen. Table XVI details the requirements for SCLK rate

for cascade lengths from 1 to 8 devices. This assumes a directly

coupled frame sync arrangement as shown in Figure 13.

Table XVI. Cascade Options

Number of Devices in Cascade

SCLK 12345678

DMCLK ✓✓✓✓✓✓✓✓

DMCLK/2 ✓✓✓✓✓✓✓✓

DMCLK/4 ✓✓✓✓XXXX

DMCLK/8 ✓✓XXXXXX

AD73311

CODEC

SDIFS

SDI

SCLK

SDO

SDOFS

TFS

SCLK

RFS

ADSP-21xx

DSP

Figure 13. Directly Coupled or Frame Sync Loop-

Back Configuration

When using the indirectly coupled frame sync configuration in

cascaded operation it is necessary to be aware of the restrictions

in sending data to all devices in the cascade. Effectively the time

allowed is given by the sampling interval (256/DMCLK) which

is 15.625 µs for a sample rate of 64 kHz. In this interval, the

DSP must transfer N × 16 bits of information where N is the

number of devices in the cascade. Each bit will take 1/SCLK

and, allowing for any latency between the receipt of the Rx

interrupt and the transmission of the Tx data, the relationship

for successful operation is given by:

256/DMCLK > ((N/SCLK) + T

INTERRUPT LATENCY

)

The interrupt latency will include the time between the ADC

sampling event and the Rx interrupt being generated in the

DSP—this should be 16 SCLK cycles.

In Cascade Mode, each device must know the number of

devices in the cascade because the Data and Mixed modes use a

method of counting input frame sync pulses to decide when they

should update the DAC register from the serial input register.

INTERFACING

The AD73311 can be interfaced to most modern DSP engines

using conventional serial port connections and an extra enable

control line. Both serial input and output data use an accompa-

nying frame synchronization signal which is active high one

clock cycle before the start of the 16-bit word or during the last

bit of the previous word if transmission is continuous. The serial

clock (SCLK) is an output from the codec and is used to define

the serial transfer rate to the DSP’s Tx and Rx ports. Two primary

configurations can be used: the first is shown in Figure 12 where

the DSP’s Tx data, Tx frame sync, Rx data and Rx frame sync

are connected to the codec’s SDI, SDIFS, SDO and SDOFS

respectively. This configuration, referred to as indirectly coupled

or nonframe sync loop-back, has the effect of decoupling the

transmission of input data from the receipt of output data. The

delay between receipt of codec output data and transmission of

input data for the codec is determined by the DSP’s software

latency. When programming the DSP serial port for this con-

figuration, it is necessary to set the Rx FS as an input and the

Tx FS as an output generated by the DSP. This configuration is

most useful when operating in mixed mode, as the DSP has the

ability to decide how many words (either DAC or control) can be

sent to the codec(s). This means that full control can be imple-

mented over the device configuration as well as updating the

DAC in a given sample interval. The second configuration

(shown in Figure 13) has the DSP’s Tx data and Rx data con-

nected to the codec’s SDI and SDO, respectively while the

DSP’s Tx and Rx frame syncs are connected to the codec’s

SDIFS and SDOFS. In this configuration, referred to as directly

coupled or frame sync loop-back, the frame sync signals are

connected together and the input data to the codec is forced to

be synchronous with the output data from the codec. The DSP

must be programmed so that both the Tx FS and Rx FS are

inputs as the codec SDOFS will be input to both. This configu-

ration guarantees that input and output events occur simulta-

neously and is the simplest configuration for operation in

normal Data Mode. Note that when programming the DSP in

this configuration it is advisable to preload the Tx register with

the first control word to be sent before the codec is taken out of

reset. This ensures that this word will be transmitted to coincide

with the first output word from the device(s).

AD73311

CODEC

SDIFS

SDI

SCLK

SDO

SDOFS

TFS

SCLK

RFS

ADSP-21xx

DSP

Figure 12. Indirectly Coupled or Nonframe Sync Loop-

Back Configuration

AD73311

–22–

REV. B

Control Register A contains a 3-bit field (DC0–2) that is pro-

grammed by the DSP during the programming phase. The default

condition is that the field contains 000b, which is equivalent to

a single device in cascade (see Table XVII). However, for

cascade operation this field must contain a binary value that is

one less than the number of devices in the cascade.

Table XVII. Device Count Settings

DC2 DC1 DC0 Cascade Length

000 1

001 2

010 3

011 4

100 5

101 6

110 7

111 8

PERFORMANCE

As the AD73311 is designed to provide high performance, low

cost conversion, it is important to understand the means by

which this high performance can be achieved in a typical applica-

tion. This section will, by means of spectral graphs, outline the

typical performance of the device and highlight some of the

options available to users in achieving their desired sample

rate, either directly in the device or by doing some post-processing

in the DSP, while also showing the advantages and disadvan-

tages of the different approaches.

Encoder Section

The encoder section samples at DMCLK/256, which gives a

64 kHz output rate for DMCLK equal to 16.384 MHz. The

noise shaping of the sigma-delta modulator also depends on the

frequency at which it is clocked, which means that the best

dynamic performance in a particular bandwidth is achieved by

oversampling at the highest possible rate. If we assume that the

signals of interest are in the voice bandwidth of dc–4 kHz, then

sampling at 64 kHz gives a spectral response which ensures good

SNR performance in the voice bandwidth, as shown in Figure 14.

FREQUENCY – kHz

–60

–150

0325

10 15 20 25 30

–100

S/N+D = 59.4951

Figure 14. FFT (ADC 64 kHz Sampling)

If sampling at 8 kHz is required, the user must implement some

post-processing in the DSP engine to band limit the signal and

decimate the samples to achieve the ultimate sampling rate of

8 kHz. Figure 15 shows the final spectral response of the

64 kHz sampled data having been digitally filtered and deci-

mated to an 8 kHz rate. The filter used was a 6th order ellip-

tical filter.

FREQUENCY – kHz

–140

0 4.00.5

1.0 1.5 2.0 2.5 3.0 3.5

–20

–60

–80

–100

–120

–40

S/N+D = 80.615918

Figure 15. FFT (ADC 8 kHz Filtered and Decimated from

64 kHz)

The device features an on-chip master clock divider circuit that

allows the sample rate to be reduced. The present choice of

clock divider options permits the device to sample at 64 kHz,

32 kHz, 21.33 kHz, 16 kHz and 12.8 kHz from a 16.384 MHz

master clock. Reducing the DMCLK rate lowers the sampling

rate of the sigma-delta modulator, which causes the noise shaping

to occur in a reduced bandwidth. The SNR performance up to

/2 will still be similar to that in the case of 64 kHz sampling,

but will be disimproved in the voice bandwidth due to the re-

duced noise shaping. Figure 16 shows this effect for a sampling

rate of 16 kHz.

FREQUENCY – kHz

–140

081

234567

–20

–60

–80

–100

–120

–40

S/N+D = 59.162677

Figure 16. FFT (ADC 16 kHz Sampling)

AD73311

–23–

REV. B

In order to produce a direct sampling rate of 8 kHz, it is

necessary to reduce the external master clock to 8.192 MHz and

to set the master clock divider to a ratio of 4, which results in a

sample rate of 8 kHz. In this case, the response of the Sinc

decimation filter may affect the response in the voice BW as its

first null occurs at 8 kHz. In Figure 17, Trace A shows how the

SNR remains approximately constant up to F

/2 regardless of

the sample rate F

; Trace B shows that the SNR achievable in

the voice BW is proportional to the sampling rate F

. These two

traces intersect at an F

of 8 kHz which is the point where F

equals the voice BW.

SAMPLING FREQUENCY

(

DMCLK/256

)

– kHz

816243240485664

S/(N+D) – dB

SNR IN VOICEBAND

(300Hz–3400Hz)

SNR IN BAND UP TO F

TRACE B

TRACE A

Figure 17. SNR vs. Sampling Frequency

If the input signal is externally band-limited, it is possible to

achieve the 8 kHz sampling rate directly from the 64 kHz

sample rate by decimating the sampled data in the DSP. This

technique will alias the band between 8 kHz and 64 kHz into

the 8 kHz band, therefore it is necessary to have good quality

external band-limiting on the input signal. Figure 18 shows the

spectral response of using this decimation technique for sample

rate reduction.

FREQUENCY – kHz

–120

0 4.00.5

1.0 1.5 2.0 2.5 3.0 3.5

–20

–60

–80

–100

–40

S/N+D = 59.545

Figure 18. FFT (ADC 8 kHz Subsampled)

Encoder Group Delay

The AD73311 implementation offers a very low level of group

delay, which is given by the following relationship:

Group Delay (Decimator) = Order × ((M–1)/2) × Tdec

where:

Order is the order of the decimator (= 3),

M is the decimation factor (= 32) and

Tdec is the decimation sample interval (= 1/2.048e6)

=> Group Delay (Decimator) = 3 × (32–1)/2 × (1/2.048e6)

= 22.7 µs

If final filtering is implemented in the DSP, the final filter’s

group delay must be taken into account when calculating overall

group delay.

Decoder Section

The decoder section updates (samples) at the same rate as the

encoder section, MCLK/256, which gives a 64 kHz rate from an

external MCLK of 16.384 MHz. Figure 19 shows the spectral

response of the decoder section sampling at 64 kHz. Again, its

sigma-delta modulator shapes the noise so it is reduced in the

voice bandwidth dc–4 kHz. For improved voiceband SNR, the

user can implement an initial anti-imaging filter, preceded by

8 kHz to 64 kHz interpolation, in the DSP.

FREQUENCY – kHz

–140

0325

10 15 20 25 30

–20

–60

–80

–100

–120

–40

S/N+D = 58.454842

Figure 19. FFT (DAC 64 kHz Sampling)

As is the case with the encoder section, voiceband SNR is re-

duced if the DMCLK rate is reduced as shown by the example

of 16 kHz sampling in Figure 20. This is due to the noise-shap-

ing of the sigma-delta modulator being compressed into a

smaller bandwidth, which increases the noise in the voice BW.

FREQUENCY – kHz

–140

08123 4

–20

–60

–80

–100

–120

–40

S/N+D = 57.441659

Figure 20. FFT (DAC 16 kHz Sampling)

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AD73311LARUZ

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Analog Front End - AFE SGL-Ch 3-5V Front-End Processor

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