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AD73311LARUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
AD73311
–33–
REV. B
DSP TX REG DEVICE 1
DEVICE 2
ADC WORD 1 *
0000 0000 0000 0000
DON'T CARE
XXXX XXXX XXXX XXXX
ADC WORD 2 *
0000 0000 0000 0000
DSP RX REG
STEP 1
DSP TX REG
DEVICE 1
DEVICE 2
CONTROL WORD 1
1 0 000 000 00010011
CONTROL WORD 2
1 0 001 000 00010011
ADC WORD 2 *
0000 0000 0000 0000
ADC WORD 1 *
0000 0000 0000 0000
DSP RX REG
STEP 2
DSP TX REG DEVICE 1
DEVICE 2
CONTROL WORD 1
1 1 000 010 00000000
CONTROL WORD 2
1 1 001 010 00000000
DON'T CARE
XXXX XXXX XXXX XXXX
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 7
DSP TX REG
DEVICE 1
DEVICE 2
CONTROL WORD 2
1 0 001 010 00000001
ADC WORD 1 *
0011 0111 1111 1111
DON'T CARE
XXXX XXXX XXXX XXXX
ADC WORD 2 *
0111 1000 0000 0000
DSP RX REG
STEP 4
DSP TX REG
DEVICE 1 DEVICE 2
CONTROL WORD 1
1 0 000 000 00010011
CONTROL WORD 2
1 0 001 010 00000001
ADC WORD 1 *
0000 0000 0000 0000
CONTROL WORD 2
1 0 000 000 00010011
DSP RX REG
STEP 3
DSP TX REG
DEVICE 1 DEVICE 2
CONTROL WORD 1
1 0 000 010 00000001
CONTROL WORD 2
1 0 001 010 00000001
ADC WORD 2 *
0111 1000 0000 0000
ADC WORD 1 *
0011 0111 1111 1111
DSP RX REG
STEP 5
DSP TX REG
DEVICE 1 DEVICE 2
CONTROL WORD 2
1 1 001 010 00000000
CONTROL WORD 1
1 0 000 010 00000001
ADC WORD 1 *
0011 0111 1111 1111
CONTROL WORD 2
1 0 000 010 00000001
DSP RX REG
STEP 6
DSP TX REG DEVICE 1
DEVICE 2
DAC WORD 2
0011 1111 1111 1111
READ WORD 1
1 1 000 010 00000001
DON'T CARE
XXXX XXXX XXXX XXXX
READ WORD 2
1 1 000 010 00000001
DSP RX REG
STEP 8
DSP TX REG DEVICE 1
DEVICE 2
DAC WORD 2
0011 1111 1111 1111
DON'T CARE
XXXX XXXX XXXX XXXX
READ WORD 2
1 1 111 010 00000001
READ WORD 1
1 1 111 010 00000001
DSP RX REG
STEP 9
DSP TX REG
DEVICE 1 DEVICE 2
DAC WORD 2
0011 1111 1111 1111
DON'T CARE
XXXX XXXX XXXX XXXX
READ WORD 1
1 1 110 010 00000001
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 10
DSP TX REG
DEVICE 1
DEVICE 2
DAC WORD 2
0011 1111 1111 1111
ADC WORD 1
0011 1111 1111 1111
READ WORD 2
1 1 111 010 00000001
ADC WORD 2
0100 0000 0000 0000
DSP RX REG
STEP 11
*ADC SAMPLES DURING PROGRAM MODE ARE INVALID.
CONTROL WORD 2
1 0 001 000 00010011
Figure 36. Programming Two AD73311s in Cascade for Mixed Mode
AD73311
–34–
REV. B
APPENDIX E
DAC Timing Control Example
The AD73311’s DAC is loaded from the DAC register contents
just before the ADC register contents are loaded to the serial
register (SDOFS going high). This default DAC load position
can be advanced in time to occur earlier with respect to the
SDOFS going high. Figure 37 shows an example of the ADC
unload and DAC load sequence. At time t
1
the SDOFS is raised
to indicate that a new ADC word is ready. Following the SDOFS
pulse, 16 bits of ADC data are clocked out on SDO in the sub-
sequent 16 SCLK cycles finishing at time t
2
where the DSP’s
SPORT will have received the 16-bit word. The DSP may
ADC WORD
DAC WORD
SE
SCLK
SDOFS
SDO
SDIFS
SDI
DAC REGISTER
UPDATE
DAC LOAD
FROM DAC REGISTER
t
6
t
4
t
5
t
3
t
2
t
1
Figure 37. DAC Timing Control
process this information and generate a DAC word to be sent to
the AD73311. Time t
3
marks the beginning of the sequence of
sending the DAC word to the AD73311. This sequence ends at
time t
4
where the DAC register will be updated from the 16 bits
in the AD73311’s serial register. However, the DAC will not be
updated from the DAC register until time t
5
which may not be
acceptable in certain applications. In order to reduce this delay
and load the DAC at time t
6
, the DAC advance register can be
programmed with a suitable setting corresponding to the
required time advance (refer to Table VIII for details of DAC
Timing Control settings).
AD73311
–35–
REV. B
Topic Page
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS (3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
SPECIFICATIONS (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 4, 5
TIMING CHARACTERISTICS (3 V) . . . . . . . . . . . . . . . . . 6
TIMING CHARACTERISTICS (5 V) . . . . . . . . . . . . . . . . . 7
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 8
Performance Graphs . . . . . . . . . . . . . . . . . . . . . . . 8, 22–24
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 12
Encoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 12
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Analog Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . 12
Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ADC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Decoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DAC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Analog Smoothing Filter & PGA . . . . . . . . . . . . . . . . . . . 14
Differential Output Amplifiers . . . . . . . . . . . . . . . . . . . . . 14
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Port (SPORT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPORT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPORT Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 15
DAC Advance Register . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Topic Page
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Resetting the AD73311 . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Control Register Tables . . . . . . . . . . . . . . . . . . . . . . . 17, 18
Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . . 19
Analog Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Digital Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interface Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 20
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Encoder Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Encoder Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Decoder Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Decoder Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . 24
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Digital Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DSP Programming Considerations . . . . . . . . . . . . . . . . . 27
DSP SPORT Configuration . . . . . . . . . . . . . . . . . . . . . . . 27
DSP SPORT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 27
APPENDIX A (Single Device Data Mode Operation) . . . . . . 28
APPENDIX B (Single Device Mixed Mode Operation) . . . . . 29
APPENDIX C (Dual Device Data Mode Operation) . . . 30, 31
APPENDIX D (Dual Device Mixed Mode Operation) . . 32, 33
APPENDIX E (DAC Timing Control Example) . . . . . . . . . . 34
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

AD73311LARUZ

Mfr. #:
Buy AD73311LARUZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE SGL-Ch 3-5V Front-End Processor
Lifecycle:
New from this manufacturer.
Delivery:
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