Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
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1. General description
The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual
buffer/line driver with output enable circuitry.
The 74AUP2T1326 is designed for logic-level translation and combines the functions of
the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output
enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume
a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a
high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output
enable inputs.
The output enable inputs (1OE and 2OE) are Schmitt trigger inputs, they switch at
different voltages for positive and negative-going signals. The difference between the
positive voltage V
T+
and the negative voltage V
T
is defined as the input hysteresis
voltage V
H
. The output enable inputs accept standard input signals and are capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals
Both V
CC(A)
and V
CC(B)
can be supplied at any voltage between 1.1 V and 3.6 V making
the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V,
1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are
referenced to V
CC(A)
and pins A, 2Y and 3Y are referenced to V
CC(B)
.
The device ensures low static and dynamic power consumption and is fully specified for
partial power down applications using I
OFF
. The I
OFF
circuitry disables the outputs,
preventing any damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 1.1 V to 3.6 V; V
CC(B)
: 1.1Vto3.6V.
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 2A exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
Rev. 2 — 3 July 2012 Product data sheet
74AUP2T1326 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 3 July 2012 2 of 17
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 Cto+85C
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP2T1326GF 40 C to +85 C XSON10 plastic extremely thin small outline package; no leads;
10 terminals; body 1 x 1.7 x 0.5 mm
SOT1081-2
Table 2. Marking
Type number Marking code
[1]
74AUP2T1326GF pf
R
pd
= Internal pull-down resistor.
Fig 1. Logic symbol
001aaj301
R
pd
R
pd
V
CC(B)
V
CC(A)
6
7
3
1OE
2OE
A
9
8
2Y
2
3Y
1Y

74AUP2T1326GF,115

Mfr. #:
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers 5ns 2.7V 250mW
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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