LTC3221/
LTC3221-3.3/LTC3221-5
10
3221f
Figure 5. Maximum Power Dissipation vs Ambient Temperature
POWER DISSIPATION (W)
2.0
3.0
1.0
1.5
2.5
0.5
0
AMBIENT TEMPERATURE (°C)
–50 –25 25 75 125 150
3221 F05
0 50 100
θ
JA
= 80°C/W
T
J
= 160°C
APPLICATIO S I FOR ATIO
WUU
U
If the standing current is too low, the FB pin becomes very
sensitive to the switching noise and will result in errors in
the programmed V
OUT
.
The compensation capacitor (C1) helps to improve the
response time of the comparator and to keep the output
ripple within an acceptable range. For best results, C1
should be between 22pF to 220pF.
Layout Considerations
Due to high switching frequency and high transient cur-
rents produced by the LTC3221 product family, careful
board layout is necessary. A true ground plane and short
to the PC board is recommended. Connecting the GND pin
(Pin 4 and Pin 7 on the DFN package) to a ground plane,
and maintaining a solid ground plane under the device
can reduce the thermal resistance of the package and PC
board considerably.
Derating Power at High Temperatures
To prevent an overtemperature condition in high power
applications, Figure 5 should be used to determine the
maximum combination of ambient temperature and power
dissipation.
The power dissipated in the LTC3221 family should always
fall under the line shown for a given ambient temperature.
The power dissipation is given by the expression:
PVVI
D IN OUT OUT
= (– )•2
This derating curve assumes a maximum thermal resis-
tance, θ
JA
, of 80°C/W for 2mm × 2mm DFN package.
This can be achieved from a printed circuit board layout
with a solid ground plane and a good connection to the
ground pins of the LTC3221 and the Exposed Pad of the
DFN package. Operation out of this curve will cause the
junction temperature to exceed 150°C which is the maxi-
mum junction temperature allowed.
Figure 4. Recommended Layout
4
5
6
V
OUT
V
OUT
3221 F04
V
IN
GND
3
2
1
PIN 7
2.2µF
2.2µF
1µF
R1 R2
(LTC3221)
connections to all capacitors will improve performance
and ensure proper regulation under all conditions. Figure 4
shows the recommended layout confi guration.
The fl ying capacitor pins C
+
and C
–
will have very high
edge rate waveforms. The large dv/dt on these pins can
couple energy capacitively to adjacent printed circuit board
runs. Magnetic fi elds can also be generated if the fl ying
capacitors are not close to the LTC3221 (i.e. the loop area
is large). To decouple capacitive energy transfer, a Faraday
shield may be used. This is a grounded PC trace between
the sensitive node and the LTC3221 pins. For a high quality
AC ground it should be returned to a solid ground plane
that extends all the way to the LTC3221.
To reduce the maximum junction temperature due to
power dissipation in the chip, a good thermal connection
