LTC3221/
LTC3221-3.3/LTC3221-5
6
3221f
The LTC3221 family uses a switched capacitor charge pump
to boost V
IN
to a regulated output voltage. Regulation is
achieved by monitoring the output voltage, V
OUT
using a
comparator (CMP in the Block Diagram) and keeping it
within a hysteresis window. If V
OUT
drops below the lower
trip point of CMP, V
OUT
is charged by the controlled cur-
rent, I
SW
in series with the fl ying capacitor C
FLY
. Once V
OUT
goes above the upper trip point of CMP, or if the upper
trip point is not reached after 0.8µs, C
FLY
is disconnected
from V
OUT
. The bottom plate of C
FLY
is then connected
to GND to allow I
SW
to replenish the charge on C
FLY
for
0.8µs. After which, I
SW
is turned off to keep the operating
supply current low. CMP continues to monitor V
OUT
and
turns on I
SW
if the lower threshold is reached again.
Shutdown Mode
The
⎯
S
⎯
H
⎯
D
⎯
N pin is a CMOS input with a threshold voltage
of approximately 0.8V. The LTC3221-3.3/ LTC3221-5 are
in shutdown when a logic low is applied to the
⎯
S
⎯
H
⎯
D
⎯
N
pin. In shutdown mode, all circuitry is turned off and the
LTC3221-3.3/ LTC3221-5 draw only leakage current from
the V
IN
supply. Furthermore, V
OUT
is disconnected from
V
IN
. Since the
⎯
S
⎯
H
⎯
D
⎯
N pin is a very high impedance CMOS
input, it should never be allowed to fl oat.
When
⎯
S
⎯
H
⎯
D
⎯
N is asserted low, the charge pump is fi rst dis-
abled, but the LTC3221-3.3/LTC3221-5 continue to draw
5µA of supply current. This current will drop to zero when
the output voltage (V
OUT
) is fully discharged to 0V.
OPERATIO
U
(Refer to Block Diagrams)
LTC3221-3.3/LTC3221-5 LTC3221
I
SW
CMP
SHDN
V
OUT
C
+
V
IN
C
–
GND
1
5
2
4
6
3
–
+
V
REF
CONTROL
I
SW
CMP
FB
V
OUT
C
+
V
IN
C
–
GND
1
5
2
4
6
–
+
V
REF
CONTROL
3
2
1
2
1
2
1
2
1
3221 BD
BLOCK DIAGRA
W
PI FU CTIO S
UUU
C+ (Pin 1): Flying Capacitor Positive Terminal.
C– (Pin 2): Flying Capacitor Negative Terminal.
⎯
S
⎯
H
⎯
D
⎯
N (Pin 3) (LTC3221-3.3/LTC3221-5): Active Low
Shutdown Input. A low on
⎯
S
⎯
H
⎯
D
⎯
N disables the LTC3221-3.3/
LTC3221-5.
⎯
S
⎯
H
⎯
D
⎯
N must not be allowed to fl oat.
FB (Pin 3) (LTC3221): Feedback. The voltage on this pin
is compared to the internal reference voltage (1.23V) by
the error comparator to keep the output in regulation. An
external resistor divider is required between V
OUT
and FB
to program the output voltage.
GND (Pin 4): Ground. Should be tied to a ground plane
for best performance.
V
IN
(Pin 5): Input Supply Voltage. V
IN
should be bypassed
with a 2.2µF low ESR capacitor.
V
OUT
(Pin 6): Regulated Output Voltage. For best perfor-
mance, V
OUT
should be bypassed with a 2.2µF or higher
low ESR capacitor as close as possible to the pin.
Exposed Pad (Pin 7) Ground. The exposed pad must be
soldered to PCB ground to provide electrical contact and
optimum thermal performance.
