STK554U362C-E
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8
Input / Output Timing Chart
Fig. 7
Notes
*1 : *1 shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for switching delay
externally.
*2 : *2 when V
DD
decreases all gate output signals will go low and cut off all 6 IGBT outputs. When V
DD
rises the operation will resume
immediately.
*3 : *3 when the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs return
to normal operation immediately after the upper side gate voltage rises.
*4 : *4 when VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2 ms (typ) after over current condition is
removed.
ON
OFF
HIN1,2,3
LIN1,2,3
ITRIP terminal
Voltage
Upper
U, V, W
Lower
U ,V, W
VB1,2,3
*1
*1
OFF
ON
*2
*3
VBS undervoltage protection reset signal
VDD undervoltage protection reset voltage
VIT≥0.54V
VIT<0.44V
utomatically reset after protection
(typ.2ms)
*4
VDD
VBS undervoltage protection reset voltage
FLTEN
