AT49BV4096A-70TI Datasheet AT49BV4096A-70TI | P4-P6

AT49BV/LV4096A

1618F–FLASH–11/02

timings are used. The address locations used in the command sequences are not

affected by entering the command sequences.

RESET: A RESET input pin is provided to ease some system applications. When

RESET

is at a logic high level, the device is in its standard operating mode. A low level

on the RESET

input halts the present device operation and puts the outputs of the

device in a high-impedance state. When a high level is reasserted on the RESET

pin,

the device returns to the read or standby mode, depending upon the state of the control

inputs. By applying a 12V ± 0.5V input signal to the RESET

pin, the boot block array can

be reprogrammed even if the boot block program lockout feature has been enabled (see

“Boot Block Programming Lockout Override” section).

ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased

state of memory bits is a logic “1”. The entire device can be erased by using the Chip

Erase command or individual sectors can be erased by using the Sector Erase

commands.

CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip

erase software code. After the chip erase has been initiated, the device will internally

time the erase operation so that no external clocks are required. The maximum time to

erase the chip is t

If the boot block lockout has been enabled, the chip erase will not erase the data in the

boot block; it will erase the main memory block and the parameter blocks only. After the

chip erase, the device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into four

sectors that can be individually erased. There are two 4K word parameter block sec-

tions, one boot block, and the main memory array block. The Sector Erase command is

a six-bus cycle operation. The sector address is latched on the falling WE

edge of the

sixth cycle while the 30H data input command is latched at the rising edge of WE

. The

sector erase starts after the rising edge of WE

of the sixth cycle. The erase operation is

internally controlled; it will automatically time to completion. Whenever the main memory

block is erased and reprogrammed, the two parameter blocks should be erased and

reprogrammed before the main memory block is erased again. Whenever a parameter

block is erased and reprogrammed, the other parameter block should be erased and

reprogrammed before the first parameter block is erased again. Whenever the boot

block is erased and reprogrammed, the main memory block and the parameter blocks

should be erased and reprogrammed before the boot block is erased again.

BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to

a logic “0”) on a byte-by-byte or word-by-word basis. Programming is accomplished via

the internal device command register and is a four-bus cycle operation. The device will

automatically generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be

ignored. If a hardware reset happens during programming, the data at the location being

programmed will be corrupted. Please note that a data “0” cannot be programmed back

to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after

the specified t

cycle time. The Data Polling feature may also be used to indicate the

end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block

that has a programming lockout feature. This feature prevents programming of data in

the designated block once the feature has been enabled. The size of the block is 8K

words. This block, referred to as the boot block, can contain secure code that is used to

bring up the system. Enabling the lockout feature will allow the boot code to stay in the

device while data in the rest of the device is updated. This feature does not have to be

AT49BV/LV4096A

1618F–FLASH–11/02

activated; the boot block’s usage as a write-protected region is optional to the user. The

address range of the boot block is 00000H to 01FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or pro-

grammed when input levels of 5.5V or less are used. Data in the main memory block

can still be changed through the regular programming method. To activate the lockout

feature, a series of six program commands to specific addresses with specific data must

be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if

programming of the boot block section is locked out. When the device is in the software

product identification mode (see Software Product Identification Entry and Exit sections)

a read from the following address location will show if programming the boot block is

locked out – 00002H. If the data on I/O0 is low, the boot block can be programmed; if

the data on I/O0 is high, the program lockout feature has been enabled and the block

cannot be programmed. The software product identification exit code should be used to

return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the

boot block programming lockout by taking the RESET

pin to 12 volts during the entire

chip erase, sector erase or word programming operation. When the RESET

pin is

brought back to TTL levels, the boot block programming lockout feature is again active.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and

manufacturer as Atmel. It may be accessed by hardware or software operation. The

hardware operation mode can be used by an external programmer to identify the correct

programming algorithm for the Atmel product.

For details, see “Operating Modes” (for hardware operation) or “Software Product Identi-

fication Entry/Exit” on page 12. The manufacturer and device codes are the same for

both modes.

DATA

POLLING: The AT49BV/LV4096A features Data Polling to indicate the end of a

program cycle. During a program cycle an attempted read of the last byte loaded will

result in the complement of the loaded data on I/O7. Once the program cycle has been

completed, true data is valid on all outputs and the next cycle may begin. During a chip

or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the

program or erase cycle has completed, true data will be read from the device. Data

Poll-

ing may begin at any time during the program cycle.

TOGGLE BIT: In addition to Data

Polling, the AT49BV/LV4096A provides another

method for determining the end of a program or erase cycle. During a program or erase

operation, successive attempts to read data from the device will result in I/O6 toggling

between one and zero. Once the program cycle has completed, I/O6 will stop toggling

and valid data will be read. Examining the toggle bit may begin at any time during a pro-

gram cycle.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-

grams to the AT49BV/LV4096A in the following ways: (a) V

sense: if V

is below

1.8V (typical), the program function is inhibited. (b) V

power on delay: once V

has

reached the V

sense level, the device will automatically time out 10 ms (typical)

before programming. (c) Program inhibit: holding any one of OE

low, CE high or WE

high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the

or CE inputs will not initiate a program cycle.

INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address and

control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affect-

ing the operation of the device. The I/O lines can only be driven from 0 to V

+ 0.6V.

AT49BV/LV4096A

1618F–FLASH–11/02

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A17 (Don’t Care).

2. The boot sector has the address range 00000H to 01FFFH.

3. Either one of the Product ID Exit commands can be used.

4. SA = sector addresses: (A17 - A0)

SA = 01XXX for BOOT BLOCK

SA = 02XXX for PARAMETER BLOCK 1

SA = 03XXX for PARAMETER BLOCK 2

SA = 3FXXX for MAIN MEMORY ARRAY

Command Definition (in Hex)

(1)

Command

Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr D

OUT

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

(4)

Byte/Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D

Boot Block Lockout

(2)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

Product ID Entry 3 5555 AA 2AAA 55 5555 90

Product ID Exit

(3)

3 5555 AA 2AAA 55 5555 F0

Product ID Exit

(3)

1xxxxF0

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

Voltage on RESET

with Respect to Ground...................................-0.6V to +13.5V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

AT49BV4096A-70TI

Mfr. #:

Buy AT49BV4096A-70TI

Manufacturer:

Microchip Technology / Atmel

Description:

NOR Flash 4M bit

Lifecycle:

New from this manufacturer.

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AT49BV4096A-70TI