8
AT49BV/LV4096A
1618F–FLASH–11/02
AC Read Waveforms
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE
may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE, whichever occurs first (C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
t
R
, t
F
< 5 ns
Output Test Load
AC Read Characteristics
Symbol Parameter
AT49LV4096A-70 AT49BV4096A-90
UnitsMin Max Min Max
t
ACC
Address to Output Delay 70 90 ns
t
CE
(1)
CE to Output Delay 70 90 ns
t
OE
(2)
OE to Output Delay 0 35 0 40 ns
t
DF
(3)(4)
CE or OE to Output Float 0 25 0 25 ns
t
OH
Output Hold from OE, CE or Address,
whichever occurred first
00ns
t
RO
RESET to Output Delay 800 800 ns
OE
RESET
CE
t
CE
t
OE
t
RO
t
ACC
t
DF
t
OH
ADDRESS
HIGH Z
OUTPUT
OUTPUT
ADDRESS VALID
VALID
2.4V
0.4V
3.3V
100 pF
OUTPUT
PIN
1.8K
1.3K