MAX3670
Layout
The MAX3670 performance can be significantly affect-
ed by circuit board layout and design. Use good high-
frequency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the reference and VCO clock signals.
Power-supply decoupling should be placed as close to
V
CC
pins as possible. Take care to isolate the input
from the output signals to reduce feedthrough.
VCO Selection
The MAX3670 is designed to accommodate a wide
range of VCO gains, positive or negative transfer
slopes, and V
CC
-referenced or ground-referenced con-
trol voltages. These features allow the user a wide
range of options in VCO selection; however, the proper
VCO must be selected to allow the clock generator cir-
cuitry to operate at the optimum levels. When selecting
a VCO, the user needs to take into account the phase
noise and modulation bandwidth. Phase noise is impor-
tant because the phase noise above the PLL bandwidth
will be dominated by the VCO noise performance.
The modulation bandwidth of the VCO contributes an
additional higher-order pole (HOP) to the system and
should be greater than the HOP set with the external fil-
ter components.
Noise Performance Optimization
Depending on the application, there are many different
ways to optimize the PLL performance. The following
are general guidelines to improve the noise on the sys-
tem output clock.
1) If the reference clock noise dominates the total sys-
tem-clock output jitter, then decreasing the loop
bandwidth (K) reduces the output jitter.
2) If the VCO noise dominates the total system clock
output jitter, then increasing the loop bandwidth (K)
reduces the output jitter.
3) Smaller total divider ratio (N1 ✕ N2), lower HOP, and
smaller R
1
reduce the spurious output jitter.
4) Smaller R
1
reduces the random noise due to the op amp.
LOL Setup
The LOL output indicates if the PLL has locked onto the
reference clock using an XOR gate and comparator.
The comparator threshold can be adjusted with THADJ,
and the XOR gate output can be filtered with a capaci-
tor between CTH and ground (Figure 3 in the
Interface
Schematic
section). When the voltage at pin CTH
exceeds the voltage at pin THADJ, then the LOL output
goes low and indicates that the PLL is not locked. Note
that excessive jitter on the reference clock input at fre-
quencies above the loop bandwidth may degrade LOL
functionality.
The user can set the amount of frequency or phase dif-
ference between VCO and reference clock at which
LOL indicates an out-of-lock condition. The frequency
difference is called the beat frequency. The CTH pin
can be connected to an external capacitor, which sets
the lowpass filter frequency to approximately
This lowpass filter frequency should be set about 10
times lower than the beat frequency to make sure the
filtered signal at CTH does not drop below the THADJ
threshold voltage. The internal compare frequency of
the part is 77.78MHz. For a 1ppm sensitivity (beat fre-
quency of 77Hz), the filter needs to be at 7.7Hz, and
CTH should be at 0.33µF.
The voltage at THADJ will determine the level at which
the LOL output flags. THADJ is set to a default value of
0.6V which corresponds in a 45° phase difference. This
value can be overridden by applying the desired
threshold voltage to the pin. The range of THADJ is
from 0V (0°) to 2.4V (180°).
