LT8584
28
8584fb
For more information www.linear.com/LT8584
applicaTions inForMaTion
RECOMMENDED LAYOUT
The potentially high voltage operation of the LT8584
demands careful attention to the board layout, observing
the following points:
1. Minimize the board trace area of the high voltage end
of the secondary winding.
2. Keep the electrical path formed by C
VTRAN
, the primary
of T1, the SW node, and ground as short as possible.
Increasing the length of this path effectively increases
the leakage inductance of T1, resulting in excessive
energy loss in the internal Zener clamp or RCD snubber.
3. Thermal vias should be added underneath the chip’s
exposed pad, pin 17, to enhance the LT8584’s thermal
performance. These vias should go directly to a local
ground plane with a minimum area of 650mm
2
.
4. Make Kelvin connections for V
SNS
, V
CELL
, and R
SNS
to
the battery cell when using the LT8584 in serial mode.
The IR drop in the battery connection can be calibrated
out using a software algorithm. Consult Application
Engineering.
5. Care should be taken when routing V
CELL
, V
SNS
and V
IN
connections. R
TRACE
in Figure 15 should be minimized for
better efficiency. R
TRACE
should never exceed 19•R
SNS
.
This guarantees that the OUT pin amplifier headroom is
sufficient enough
for reporting the
V
SNS
amplifier output.
6. Minimize the total connection resistance from the battery
terminals to the V
CELL
and GND pins of the LT8584. It
is recommended to keep the total resistance less than
60mΩ to improve converter efficiency. Excessive IR
drops in the PCB traces or connector terminals could
also cause the LT8584 to prematurely enter UVLO.
CONNECTING TO A BATTERY STACK MONITOR
There are two methods used to connect the LT8584 bal
-
ancer to a battery stack monitor (BSM): either a single-wire
or two-wire. Both have advantages and disadvantages.
Both methods may require Kelvin connections for the
BSM supply rails depending upon the magnitude of IR
drop across the connections to the battery stack. In most
cases, keeping the individual connection resistances less
than 60mΩ allows the BSM supply rails to share the return
path through RW0 and RW12, see Figure 16.
The single-wire connection is recommended due to com
-
plete system visibility of the wire connection impedance.
The single-wire is also cheaper and more reliable due to
fewer wire connections. See the Typical Application section
for proper Kelvin connection between adjacent LT8584
channels in single-wire mode.
Note that in the
two-wire connection scheme, the ground
connection
impedance can not be determined when
calculating wire impedance and will be invisible to the
measurement system. On the flip side, the algorithms
for computing two-wire connection impedance and back
calculating V
CELL
during discharging are more straightfor-
ward. The two-wire method also has the advantage of only
losing
visibility of a single cell during an open connection
instead of two as in the single-wire method.
INTEGRATING WITH THE LTC680x FAMILY
The LTC680x family of parts are multi-cell battery stack
monitors that are described in the Operation section of
this data sheet. For more information, consult the LTC680x
data sheets. Several operational flavors are available with
their inherent differences shown in Table 9.
Table 9. LTC680x Feature Differences
PART COMMUNICATION COMPATIBLE MODES
LTC6802-1 Daisy Chained Serial Simple Mode Only
LTC6802-2 Addressable Parallel Simple Mode Only
LTC6804-1/LTC6803-1/
LTC6803-3
Daisy Chained Serial Serial / Simple Mode
LTC6804-2/LTC6803-2/
LTC6803-4
Addressable Parallel Serial / Simple Mode
V
BAT
+
–
SNS
V
CELL
V
SNS
I
SW
TRACE
V
IN
•
L
Q1
Figure 15. R
TRACE
Minimization
