Philips Semiconductors Product data sheet
SC28L194Quad UART for 3.3 V and 5 V supply voltage
2006 Aug 15
45
SCLK
IACKN
CEN
W_RN
ADDRESS
DATA
DACKN
INVALID
DON’T CARE
C1 C2 C3 C4
VALID
t
CS
t
RWS
t
AS
t
AH
t
DD
DAK
DLY
C4
DAK
DLY
CEN
HIGH
t
DF
INVALID
INVALIDINVALID
DON’T CARE
NOTE: CEN must not be active during an IACKN cycle. If CEN is active, IACKN will be ignored
and a normal read or write will be executed according to W_RN. In the synchronous
mode, extended IACKN signal will start another IACKN. (This may not be desired, but
is allowed.)
SD00525
Figure 8. Basic IACKN Cycle, ASYNC/SYNC
C1 and C2 should be chosen according to the
crystal manufacturer’s specification.
C1 and C2 values will include any parasitic
capacitance of the wiring.
f
X1
+5V
1K required for
TTL gate.
X1
X2
C1 = C2 = 24pF FOR C
L
= 20pF
X1
X2
3.6864MHz
3pF
4pF
50 KOHMs
TO
150 KOHMs
28C194
NOTES:
C1 and C2 should be based on manufacturer’s specification.
X1 and X2 parasitic capacitance IS 1-2pF AND 3-5pF, respectively.
GAIN: at 4MHz 8 to 14db; at 8MHz 2 to 6db
PHASE: at 4MHz 272° to 276°; at 8MHz 272° to 276°
The above figures for 5V operation. Operation at 3V is to be determined.
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY: 2 – 4MHZ
LOAD CAPACITANCE (C
L
): 12 – 32pF
TYPE OF OPERATION: PARALLEL RESONANT, FUNDAMENTAL MODE
NC
C1
C2
MUX
To
remainder
of circuit
÷ 2
38.4kHz CLOCK
BRG
TO I/O CHANGE-OF-STATE DETECTORS
22
STANDARD
BAUD
RATES
X1 L/H
T/R f
X1
SD00670
Figure 9. X1/X2 Communication Crystal Clock
