CAV24M01
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8
READ OPERATIONS
Immediate Address Read
In standby mode, the CAV24M01 internal address counter
points to the data byte immediately following the last byte
accessed by a previous operation. If that ‘previous’ byte was
the last byte in memory, then the address counter will point
to the 1st memory byte, etc.
When, following a START, the CAV24M01 is presented
with a Slave address containing a ‘1’ in the R/W
bit position
(Figure 10), it will acknowledge (ACK) in the 9th clock cycle,
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address counter.
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W
bit set to ‘0’)
and the desired two byte address. Instead of following up
with data, the Master then issues a 2nd START, followed by
the ‘Immediate Address Read’ sequence, as described
earlier.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAV24M01, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap−around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
Figure 10. Immediate Address Read Timing
SCL
SDA 8th Bit
STOPNO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
Figure 11. Selective Read Timing
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
T
SLAVE
S
A
C
K
S
T
A
R
T
P
S
T
O
P
BYTE ADDRESS
ADDRESS
N
O
A
C
K
DATA
BUS ACTIVITY:
MASTER
SDA LINE
a
15
− a
8
a
7
− a
0
Figure 12. Sequential Read Timing
S
T
O
P
P
SLAVE
ADDRESS
A
C
K
N
O
A
C
K
DATA n
BUS ACTIVITY:
MASTER
SDA LINE
A
C
K
DATA n+1 DATA n+2
A
C
K
A
C
K
DATA n+x
