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544M-01LF

P1-P3P4-P6P7-P7
DATASHEET
CLOCK DIVIDER ICS544-01
IDT®
CLOCK DIVIDER 1
ICS544-01 REV B 051810
Description
The ICS544-01 is crystal oscillator module IC with
divide by 512 frequency output. It employs a 16.777216
MHz fundamental frequency crystal source oscillator to
generate 32.768 kHz output crystal oscillator output. In
addition a divide by 256, 64 and 32 options are also
provided through select pins. The chip has an OE pin
that tri-states the output and stops the oscillator circuits.
The ICS544-01 is a member of IDT’s ClockBlocks
TM
family of clock building blocks. See the ICS541 and
ICS542 for other clock dividers, and the ICS501, 502,
511, 512, and 525 for clock multipliers.
Features
• Packaged in 8-pin SOIC
• Pb-free package
• IDT’s lowest cost clock divider
• Easy to use with other generators and buffers
• Input crystal at 16.777216MHz
• Output clock duty cycle of 45/55
• Output Enable
• Advanced, low-power CMOS process
• Operating voltage of 2.25 V to 3.6 V
• Does not degrade phase noise - no PLL
• Available in industrial temperature range
Block Diagram
Divider and
Selection
Circuitry
/32, /64
/256, /512,
CLK1
OE
GND
VDD
X1
X2
16.777216MHz
crystal input
Optional tuning
capacitors
S1, S0 (1:0)
ICS544-01
CLOCK DIVIDER CLOCK DIVIDER
IDT®
CLOCK DIVIDER 2
ICS544-01 REV B 051810
Pin Assignment
8-pin (150 mil) SOIC
Clock Divider Table
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
External Components
Series Termination Resistor
Ω
Ω
Ω
On chip capacitors
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C
L
-12)*2 in this equation,
C
L
=crystal load capacitance in pf. For example, for a
crystal with a 16 pF load cap, each external crystal cap
would be 8 pF. [(16-12)x2]=8.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS544-01 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
X1/ICLK
X2
GND
VDD
S0
OE
CLK
S11
2
3
4
8
7
6
5
S1 S0 CLK
0 0 Input/32
0 1 Input/64
10 Input/256
11 Input/512
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 X1/ICLK XI Crystal input.
2 X2 Xo Connect to crystal for crystal input and leave open for clock input.
3 GND Power Connect to ground.
4 S0 Input
Select 0 for output clock. Connect to GND or VDD, per divider table above.
Internal pull-up resistor.
5 CLK Output Clock output per table above. Internal Pull down resistor.
6 OE Input
Output Enable.Tri-states output clock when low. Also shuts down the oscillator
circuit. Internal pull-up resistor. OE=1 normal operation.
7 VDD Power Connect to 2.25 V to 3.6 V.
8 S1 Input
Select 1 for output clock. Connect to GND or VDD, per divider table above.
Internal pull-up resistor.
ICS544-01
CLOCK DIVIDER CLOCK DIVIDER
IDT®
CLOCK DIVIDER 3
ICS544-01 REV B 051810
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the VDD
pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS544-01. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS544-01. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial) 0 to +70° C
Ambient Operating Temperature (industrial) -40 to +85° C
Storage Temperature -65 to +150° C
Junction Temperature 125° C
Soldering Temperature 260° C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature (commercial) 0 +70 ° C
Ambient Operating Temperature (industrial) -40 +85 ° C
Power Supply Voltage (measured in respect to GND) 2.25 3.6 V
P1-P3P4-P6P7-P7

544M-01LF

Mfr. #:
Buy 544M-01LF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution CLOCK DIVIDER
Lifecycle:
New from this manufacturer.
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