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Copyright © 2009 Microsemi
Rev. 1.3 2009-02-23 Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
7
PD Operating Status LED1 LED2
IEEE802.3af – ON ON OFF
IEEE802.3at – ON ON ON
IEEE802.3af -
OVL/SC
Blink at 1Hz OFF
IEEE802.3at -
OVL/SC
Blink at 1Hz Blink at 1Hz
Vmain out of range Blink at 4Hz OFF
Layout Design Guidelines
(See Figure 3 for layout example)
Isolation & Termination
– as specified in the IEEE
standard, certain isolation requirements need to be
met in all PoE equipment. In addition, EMI limitations
should be considered, according to FCC and
European EN regulations.
These requirements are taken into account by PoE
switch vendors, while designing the switch circuitry.
However, when a PoE device is integrated into a
switch, special design considerations must be taken
into account, due to the unique combination of Data
and Power circuitries.
The next paragraphs define these requirements and
provide recommendations for their implementation,
so as to assist designers in meeting those
requirements and in integrating PoE Chipset.
Isolation
- As specified in the IEEE standard,
1500Vac rms isolation is required between the main
board circuitry of the switch, including protective and
frame ground and the PoE circuitry.
Isolating the Stacked Modular Jack Assembly
The IEEE standard requires 1500 Vrms isolation
between PoE voltages and frame ground (EGND).
Note that RJ-45 jack assemblies may have a metal
cover that reach almost to the PCB surface.
Proper traces clearance (at least 80 mils) are to be
maintained between EGND traces for the RJ-45
modular jack assembly metal covering and adjacent
circuit paths and components.
To prevent 1500 Vrms isolation violation, it is
necessary to provide layout clearances of PoE
traces, on the top layer, in the vicinity of the RJ-45
connector assemblies.
PoE Output Ports’ Filtering and Terminations:
A
switch normally creates a noisy environment. In
order to meet the EMI requirements, good filtering
and line terminations may be needed when
connecting the PoE circuit outputs to the switch
circuitry (see Figure 1). Note that in most PoE
systems, it is recommended to use 0 Ohms resistors
for R100 and R101. However, certain systems may
benefit from the 75Ohm value. It is recommended
that filtering provisions are utilized.
A circuitry for the recommended filter includes:
A common mode choke for conducted EMI
performances
Output differential capacitor filter for
radiated EMI performances
Y-capacitive/resistive network to chassis
Since each system is a unique EMI case, this circuit
is a good starting point for EMI suppression.
Out (+)
Out (-)
Port_Pos
Port_Neg
R100 R101
C100
C101
L100
C102 C103
Figure 1: Recommended EMI Filter
Note For best EMI performance and to avoid additional
noise accumulated on the lines between the filter
and the port connectors, it is recommended to
assemble this circuitry as close as possible to the
port connectors.
PoE circuitry Trace Clearance - PoE technology
involves voltages as high as 57VDC. Thus, plan
adjacent traces for 100V operational creepage.
Operational creepage should be maintained to
prevent breakdown between traces carrying these
potentials.
Locating PoE Circuitry in a Switch
- Placement of the
PoE circuitry must be as close as possible to the
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Copyright © 2009 Microsemi
Rev. 1.3 2009-02-23 Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
8
switch’s pulse transformers, to minimize the length of
high current traces as well as RFI pick-up.
Ground & Power Planes
- As the Chipset PoE
solution is a mixed-signal (analog and digital)
circuitry, special care must be taken when routing
the ground and power signals lines. Ground planes
are crucial for proper operation and should be
designed in accordance with the following
guidelines:
Separate analog and digital grounds, with
a gap of at least 40 mils.
Earth ground is used to tie in the metal
frame of the RJ-45 connectors. This
ground is to be routed separately and
connected to the switch’s metal
chassis/enclosure
Only a single connection point is to be
used between the digital and analog
grounds, in order to prevent ground loop
currents. This connection is to be
accomplished near the current loop
senses resistors R9, R11
The traces from Vmain input to the port
output, PoE switch (Q4) and sense
resistors must be designed to carry 1A
continuous current
Peripheral Components –
To prevent hot spots on the peripheral
components minimum distance of 5mm
should be maintained between the
powering Zener diodes D1 and D3, the
linear regulator U1, sense resistors R9 and
R11 (placed together) and current limit
MOSFET Q4. Other methods may be used
in order to dissipate the heat, such as
thermal copper planes at the top and
bottom layers with heat transfer vias
between them
Filtering capacitors for Vcc (U4 pins 5, 15)
are to be located close to these pins
The input and output capacitors of the
linear regulator should be placed close to
the regulator pins
The trace connecting the power MOSFET
and the sense resistors should be as short
as possible and the current loop sampling
trace should be connected as close as
possible to the sense resistors
Specifying PoE Power Supply_____
An intelligent selection of the power supply to be
used in conjunction with the 1-port system may avoid
the use of additional filtering circuitry (e.g. Front End
Common Mode filter) for standard regulatory
approval.
Electromagnetic compatibility requirements
Typical Power over Ethernet (PoE) technology
systems are classified in most applications as
Information Technology Equipment (I.T.E).
The I.T.E should comply with three tests in order to
get a standard approval:
Conducted disturbance at mains ports (AC
input)
Radiated disturbance at a measuring
distance of 10m
Conducted common mode disturbance at
telecommunication ports (output port
containing Ethernet+Power)
A relatively new requirement of EN55022
that is mandatory as of August 1st, 2007
In most cases, the PSE side of a PoE system
incorporates a main AC to DC Switching Mode
Power Supply (SMPS) required for delivery of a DC
power to the PoE ports.
This power supply is most likely to be the largest
source for common mode noise injection on the
output ports wires, as its noisy output voltage is
super-imposed on the telecommunication wires by
the PoE control circuitry. The common mode noise is
generated by the high dv/dt and dI/dt switching rates
in power MOSFETs and high speed rectifying
diodes, common in SMPS designs.
As the system designer is usually responsible for
specifying this power supply, it is important to add
the standard requirements to the power supply
specifications and specify a specific reference test
setup to be used for the tests.
This reference test setup should be as similar as
possible to the final product, which means using the
same box material (plastic or metal) and the same
distance and polarity between the SMPS and PoE
circuitry.
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Copyright © 2009 Microsemi
Rev. 1.3 2009-02-23 Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
9
When specifying and testing the power supply, it is
important to assure that test requirements are met
under all load conditions and line voltages.
Most switching power supplies designs will exhibit
the highest conducted noise at the maximum load
and the lowest line voltage.
However, other cases may also exist. As it is
impractical to go through all loads span, it is
recommended to test at full load, medium load and
minimum load.
The cables suggested for use are Cat 5 UTP cables
of at least 5m. (Both UTP and FTP cables shall be
tested for compliance in the final system tests).
Note that the standard deals with shielded and un-
shielded cables independently and the appropriate
test procedure shall be performed.
Resistive loads are selected to remove possible
noise injection from the PD side, leaving only the
main power supply as the source of noise.
For radiated disturbance using a proper SMPS
layout (short power patch and avoiding current
loops) may contribute to disturbance reduction.
For additional reduction if needed, full or partial
metal frame connected to mains earth may be used.
Immunity requirements –
An I.T.E should comply with EN55024 in order to get
a standard approval:
Most power supply manufacturers are familiar with
the standard requirements from the power supply
and know how to design the power supply to comply
with it. The requirements from the power supply's AC
input power port are:
Immunity to radio frequency continuous
conducted according to IEC61000-4-6
Voltage dips and voltage interruptions
according to IEC61000-4-11
Surges according to IEC61000-4-5
Fast transients according to IEC61000-4-4
The PoE circuitry may also be exposed
to immunity tests on the
telecommunication ports such as:
Radio frequency continuous conducted
according to IEC61000-4-6
Surge line to earth according to IEC61000-
4-5 (usually for port that may connect to
outdoor cables)
Fast transients according to IEC61000-4-4
and the PoE enclosure port exposed to:
Radio frequency electromagnetic field
immunity according to IEC61000-4-3
ESD electrostatic-discharge according to
IEC61000-4-2
To satisfy these tests requirements on the
telecommunication lines, "Y" capacitors to the
chassis (earth) will create a current path to earth.
It is a good practice to have two "Y" capacitors of
10nF/2000V each at the power supply output
positive and negative nodes to earth, to create a
current path for surge generated on the
telecommunication lines (respect to earth).
The system may benefit from two small "Y"
1nF/2000V capacitors, on the PoE positive and
negative output lines close to the output RJ45
connector, by increasing system immunity to ESD.

PD-IM-7301

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Ethernet Development Tools PoE EVB
Lifecycle:
New from this manufacturer.
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