LTC1046
6
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A
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LV (Pin 6)
The internal logic of the LTC1046 runs between V
+
and LV
(Pin 6). For V
+
greater than or equal to 3V, an internal
switch shorts LV to GND (Pin 3). For V
+
less than 3V, the
LV pin should be tied to ground. For V
+
greater than or
equal to 3V, the LV pin can be tied to ground or left floating.
OSC (Pin 7) and BOOST (Pin 1)
The switching frequency can be raised, lowered or driven
from an external source. Figure 5 shows a functional
diagram of the oscillator circuit.
By connecting the BOOST (Pin 1) to V
+
, the charge and
discharge current is increased and, hence, the frequency
is increased by approximately three times. Increasing the
frequency will decrease output impedance and ripple for
higher load currents.
Loading Pin 7 with more capacitance will lower the fre-
quency. Using the BOOST pin in conjunction with external
capacitance on Pin 7 allows user selection of the fre-
quency over a wide range.
Driving the LTC1046 from an external frequency source
can be easily achieved by driving Pin 7 and leaving the
BOOST pin open, as shown in Figure 6. The output current
from Pin 7 is small, typically 15µA, so a logic gate is
capable of driving this current. The choice of using a CMOS
logic gate is best because it can operate over a wide supply
voltage range (3V to 15V) and has enough voltage swing
to drive the internal Schmitt trigger shown in Figure 5. For
5V applications, a TTL logic gate can be used by simply
adding an external pull-up resistor (see Figure 6).
Capacitor Selection
While the exact values of C
IN
and C
OUT
are noncritical,
good quality, low ESR capacitors such as solid tantalum
are necessary to minimize voltage losses at high currents.
For C
IN
the effect of the ESR of the capacitor will be
multiplied by four, due to the fact that switch currents are
approximately two times higher than output current, and
losses will occur on both the charge and discharge cycle.
This means that using a capacitor with 1Ω of ESR for C
IN
will have the same effect as increasing the output imped-
ance of the LTC1046 by 4Ω. This represents a significant
increase in the voltage losses. For C
OUT
the effect of ESR
is less dramatic. C
OUT
is alternately charged and dis-
charged at a current approximately equal to the output
current, and the ESR of the capacitor will cause a step
function to occur, in the output ripple, at the switch
transitions. This step function will degrade the output
regulation for changes in output load current, and should
be avoided. Realizing that large value tantalum capacitors
can be expensive, a technique that can be used is to
parallel a smaller tantalum capacitor with a large alumi-
num electrolytic capacitor to gain both low ESR and
reasonable cost. Where physical size is a concern some
of the newer chip type surface mount tantalum capacitors
can be used. These capacitors are normally rated at
working voltages in the 10V to 20V range and exhibit very
low ESR (in the range of 0.1Ω).
Figure 6. External Clocking
C2
V
+
100k
OSC INPUT
REQUIRED FOR TTL LOGIC
–(V
+
)
1046 F06
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
–
LTC1046
C1
NC
+
+
Figure 5. Oscillator
OSC
(7)
1046 F05
LV
(6)
BOOST
(1)
∼14pF
I2I
I2I
V
+
SCHMITT
TRIGGER
