LTC1046CN8#PBF

7
LTC1046
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Figure 7. Negative Voltage Converter
Negative Voltage Converter
Figure 7 shows a typical connection which will provide a
negative supply from an available positive supply. This
circuit operates over full temperature and power supply
ranges without the need of any external diodes. The LV pin
(Pin 6) is shown grounded, but for V
+
3V, it may be
floated, since LV is internally switched to GND (Pin 3) for
V
+
3V.
The output voltage (Pin 5) characteristics of the circuit are
those of a nearly ideal voltage source in series with an 27
resistor. The 27 output impedance is composed of two
terms: 1) the equivalent switched capacitor resistance
(see Theory of Operation), and 2) a term related to the ON
resistance of the MOS switches.
At an oscillator frequency of 30kHz and C1 = 10µF, the first
term is:
R=
1
f/2
EQUIV
OSC
()
=
=
••
.
C1
1
15 10 10 10
67
36
Ω.
Notice that the equation for R
EQUIV
is not a capacitive
reactance equation (X
C
= 1/ωC) and does not contain a 2π
term.
The exact expression for output impedance is complex,
but the dominant effect of the capacitor is clearly shown on
Figure 8. Voltage Doubler
Figure 9. Ultraprecision Voltage Divider
the typical curves of output impedance and power effi-
ciency versus frequency. For C1 = C2 = 10µF, the output
impedance goes from 27 at f
OSC
= 30kHz to 225 at
f
OSC
= 1kHz. As the 1/fC term becomes large compared to
switch ON resistance term, the output resistance is deter-
mined by 1/fC only.
Voltage Doubling
Figure 8 shows a two diode, capacitive voltage doubler.
With a 5V input, the output is 9.1V with no load and 8.2V
with a 10mA load.
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
LTC1046
10µF
10µF
1046 F07
V
+
1.5V TO 6V
V
OUT
= –V
+
REQUIRED FOR V
+
< 3V
T
MIN
T
A
T
MAX
+
+
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
LTC1046
10µF10µF
V
D
V
D
+
+
1046 F08
V
+
1.5V TO 6V
V
OUT
= 2
(V
IN
–1)
REQUIRED
FOR
V
+
< 3V
+ +
Ultraprecision Voltage Divider
An ultraprecision voltage divider is shown in Figure 9. To
achieve the 0.0002% accuracy indicated, the load current
should be kept below 100nA. However, with a slight loss
in accuracy, the load current can be increased.
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
LTC1046
C1
10µF
C2
10µF
T
MIN
T
A
T
MAX
I
L
100nA
REQUIRED FOR V
+
< 6V
1046 F09
V
+
3V TO 12V
+
+
±0.002%
V
+
2
LTC1046
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Battery Splitter
A common need in many systems is to obtain positive and
negative supplies from a single battery or single power
supply system. Where current requirements are small, the
circuit shown in Figure 10 is a simple solution. It provides
symmetrical positive or negative output voltages, both
Figure 10. Battery Splitter
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
LTC1046
C1
10µF
V
B
9V
C2
10µF
OUTPUT COMM0N
REQUIRED FOR V
B
< 6V
3V V
B
12V
1046 F10
+V
B
/2
4.5V
–V
B
/2
4.5V
+
+
equal to one half the input voltage. The output voltages are
both referenced to Pin 3 (output common). If the input
voltage between Pin 8 and Pin 5 is less than 6V, Pin 6
should also be connected to Pin 3, as shown by the
dashed line.
Paralleling for Lower Output Resistance
Additional flexibility of the LTC1046 is shown in Figures 11
and 12. Figure 11 shows two LTC1046s connected in
parallel to provide a lower effective output resistance. If,
however, the output resistance is dominated by 1/fC1,
increasing the capacitor size (C1) or increasing the fre-
quency will be of more benefit than the paralleling
circuit shown.
Figure 12 makes use of “stacking” two LTC1046s to
provide even higher voltages. In Figure 12, a negative
voltage doubler or tripler can be achieved depending upon
how Pin 8 of the second LTC1046 is connected, as shown
schematically by the switch.
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
LTC1046
C1
10µF
C1
10µF
+
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
LTC1046
1/4 CD4077
+
C2
20µF
1046 F11
V
OUT
= –(V
+
)
OPTIONAL SYNCHRONIZATION
CIRCUIT TO MINIMIZE RIPPLE
V
+
+
Figure 11. Paralleling for 100mA Load Current
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
LTC1046
V
+
10µF
C1
10µF
–(V
+
)
+
1
2
3
4
8
7
6
5
V
+
OSC
LV
V
OUT
BOOST
CAP
+
GND
CAP
LTC1046
FOR V
OUT
= –2V
+
FOR V
OUT
= –3V
+
+
10µF10µF
1046 F12
V
OUT
++
Figure 12. Stacking for Higher Voltage
9
LTC1046
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PACKAGE
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J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
J8 0801
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
3.175
MIN
.100
(2.54)
BSC
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457)
0° – 15°
.005
(0.127)
MIN
.405
(10.287)
MAX
.220 – .310
(5.588 – 7.874)
12
3
4
87
65
.025
(0.635)
RAD TYP
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
.045 – .065
(1.143 – 1.651)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
OBSOLETE PACKAGE

LTC1046CN8#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Switched Cap Volt Conv 50mA
Lifecycle:
New from this manufacturer.
Delivery:
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