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AD1933YSTZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
AD1933 Data Sheet
Rev. E | Page 6 of 28
TIMING SPECIFICATIONS
−40°C < T
C
< +125°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET
t
MH
MCLK duty cycle DAC clock source = PLL clock @ 256 f
S
, 384 f
S
,
512 f
S
, and 768 f
S
40 60 %
t
MH
DAC clock source = direct MCLK @ 512 f
S
(bypass on-chip PLL)
40 60 %
f
MCLK
MCLK frequency PLL mode, 256 f
S
reference 6.9 13.8 MHz
f
MCLK
Direct 512 f
S
mode 27.6 MHz
t
PDR
RST
low 15 ns
t
PDRR
RST
recovery Reset to active output 4096 t
MCLK
PLL
Lock Time MCLK and LR clock input 10 ms
256 f
S
VCO Clock, Output Duty Cycle
MCLKO/XO Pin
40 60 %
SPI PORT See Figure 9
t
CCH
CCLK high 35 ns
t
CCL
CCLK low
35
ns
f
CCLK
CCLK frequency f
CCLK
= 1/t
CCP
, only t
CCP
shown in Figure 9 10 MHz
t
CDS
CIN setup To CCLK rising 10 ns
t
CDH
CIN hold From CCLK rising 10 ns
t
CLS
CLATCH
setup To CCLK rising 10 ns
t
CLH
CLATCH
hold From CCLK rising 10 ns
t
CLHIGH
CLATCH
high
Not shown in Figure 9
10
ns
t
COE
COUT enable From CCLK falling 30 ns
t
COD
COUT delay From CCLK falling 30 ns
t
COH
COUT hold From CCLK falling, not shown in Figure 9 30 ns
t
COTS
COUT tristate From CCLK falling 30 ns
DAC SERIAL PORT See Figure 16
t
DBH
DBCLK high Slave mode 10 ns
t
DBL
DBCLK low Slave mode 10 ns
t
DLS
DLRCLK setup
To DBCLK rising, slave mode
10
ns
t
DLH
DLRCLK hold From DBCLK rising, slave mode 5 ns
t
DLS
DLRCLK skew From DBCLK falling, master mode −8 +8 ns
t
DDS
DSDATA setup To DBCLK rising 10 ns
t
DDH
DSDATA hold From DBCLK rising 5 ns
AUXTDM SERIAL PORT See Figure 17
t
ABH
AUXTDMBCLK high Slave mode 10 ns
t
ABL
AUXTDMBCLK low Slave mode 10 ns
t
ALS
AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns
t
ALH
AUXTDMLRCLK hold
From AUXTDMBCLK rising, slave mode
5
ns
t
ALS
AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns
t
DDS
DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns
t
DDH
DSDATA hold From AUXTDMBCLK rising, not shown in Figure 17 5 ns
AUXILIARY INTERFACE
t
DXDD
AUXDATA delay From AUXBCLK falling 18 ns
t
XBH
AUXBCLK high 10 ns
t
XBL
AUXBCLK low 10 ns
t
DLS
AUXLRCLK setup To AUXBCLK rising 10 ns
t
DLH
AUXLRCLK hold From AUXBCLK rising 5 ns
Data Sheet AD1933
Rev. E | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
Analog (AVDD) −0.3 V to +3.6 V
Digital (DVDD)
−0.3 V to +3.6 V
VSUPPLY −0.3 V to +6.0 V
Input Current (Except Supply Pins) ±20 mA
Analog Input Voltage (Signal Pins) −0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V
Operating Temperature Range (Case) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
represents thermal resistance, junction-to-ambient;
θ
JC
represents thermal resistance, junction-to-case. All
characteristics are for a 4-layer board.
Table 9. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
64-Lead LQFP 47 11.1 °C/W
ESD CAUTION
AD1933 Data Sheet
Rev. E | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
64
NC
63
AVDD
62
LF
61
NC
60
NC
59
NC
58
NC
57
NC
56
NC
55
NC
54
NC
53
CM
52
AVDD
51
NC
50
NC
49
DVDD
17
DSDATA3
18
DSDATA2
19
DSDATA1
20
DBCLK
21
DLRCLK
22
VSUPPLY
23
VSENSE
24
VDRIVE
25
AUXDATA1
26
NC
27
AUXTDMBCLK
28
AUXTDMLRCLK
29
CIN
30
COUT
31
DVDD
32
AGND
1
MCLKI/XI
2
MCLKO/XO
3
AGND
4
AVDD
5
OL3P
6
OL3N
7
OR3P
8
OR3N
9
OL4P
10
OL4N
11
OR4P
12
OR4N
13
RST
14
DSDATA4
15
DGND
16
AGND
48
FILTR
47
AGND
46
AVDD
45
AGND
44
OR2N
43
OR2P
42
OL2N
41
OL2P
40
OR1N
39
OR1P
38
OL1P
36
CLATCH
35
CCLK
34
DGND
33
OL1N
37
AD1933
TOP VIEW
(Not to Scale)
DIFFERENTIAL
OUTPUT
NC = NO CONNECT
06624-002
Figure 2. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Input/Output Mnemonic Description
1 I AGND Analog Ground.
2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input.
3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output.
4 I AGND Analog Ground.
5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
6 O OL3P DAC 3 Left Positive Output.
7 O OL3N DAC 3 Left Negative Output.
8 O OR3P DAC 3 Right Positive Output.
9 O OR3N DAC 3 Right Negative Output.
10 O OL4P DAC 4 Left Positive Output.
11 O OL4N DAC 4 Left Negative Output.
12 O OR4P DAC 4 Right Positive Output.
13 O OR4N DAC 4 Right Negative Output.
14 I
RST
Reset (Active Low).
15 I/O DSDATA4 DACSerial Data Input 4. Input to DAC4 data in/TDM DAC2 data out (dual-line mode)/AUX
DAC2 data out (to external DAC2).
16 I DGND Digital Ground.
17 I DVDD Digital Power Supply. Connect to digital 3.3 V supply.
18 I/O DSDATA3 DAC Serial Data Input 3. Data input to DAC3 in/TDM DAC2 data in (dual-line mode)/AUX
not used.
19 I/O DSDATA2 DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX not used.
20
I
DSDATA1
DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/AUX TDM data in.
21
I/O
DBCLK
Bit Clock for DACs. Regular stereo, TDM, or daisy-chain TDM mode.
22 I/O DLRCLK LR Clock for DACs. Regular stereo, TDM, or daisy-chain TDM mode.
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AD1933YSTZ-RL

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Digital to Analog Converters - DAC IC 8 CHAudio w/on chip PLL
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