PL580-35OC-R Datasheet PL580-39OC, PL580-39QI, PL580-37OC | P1-P3

(Preliminary)

38MHz to 320MHz Low Phase Noise VCXO

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 8/19/09 Page 1

FEATURES

 Typical 0.4ps RMS (12kHz to 20MHz) phase

jitter for.

 Typical 25ps (typ.) peak to peak jitter.

 Low phase noise output (@ 1MHz frequency

offset

o -144dBc/Hz for 155.52MHz

o -140dBc/Hz for 311.04MHz

 19MHz to 40MHz crystal input.

 38MHz to 320MHz output.

 Available in LVPECL, LVDS, or LVCMOS

outputs.

 No external varicap required.

 Output Enable selector.

 Wide pull range (±200ppm).

 3.3V operation.

 Available in 3x3 QFN or 16-pin TSSOP

packages.

DESCRIPTION

The PL580-3X is a monolithic low jitter and low phase

noise VCXO, capable of 0.4ps RMS phase jitter and

LVCMOS, LVDS, or LVPECL outputs, covering a wide

frequency output range up to 320MHz. It allows the

control of the output frequency with an input voltage

(VCON), using a low cost crystal.

The frequency selector pads of the PL580-3X enable

output frequencies of (2, 4, 8, or 16) * F

XIN

. The PL580-

3X is designed to address the demanding requirements

of high performance applications such as SONET, GPS,

Video, etc.

PACKAGE PIN ASSIGNMENT

16-pin TSSOP

3x3 QFN

Note1: QBAR is used for single ended LVCMOS output.

Note2: ^ Denotes internal pull up resistor.

BLOCK DIAGRAM

VDDANA

XIN

XOUT

SEL2^

OE_CTRL

VCON

GNDANA

SEL0^

GNDBUF

SEL1^

GNDBUF

QBAR

VDDBUF

GNDBUF

VDDBUF

QBAR

XIN

SEL0^

SEL1^

VDDANA

SEL2^

XOUT

OE_CTRL

VCON

GNDANA

GNDBUF

12 11 10 9

1 2 3

(Preliminary)

38MHz to 320MHz Low Phase Noise VCXO

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 8/19/09 Page 2

OUTPUT ENABLE LOGIC LEVELS

Part # OE State

0 (Default) Output enabled

PL580-38 (LVPECL)

1 Tri-state

0 Tri-state

PL580-35 (LVPECL)

PL580-37 (LVCMOS)

PL580-39 (LVDS)

1 (Default) Output enabled

Note: Connect to VDD to set to "1", connect to GND to set to "0".

In case of "0 (Default)" an internal pull-down resistor will set to "0" when pin is left open.

In case of "1 (Default)" an internal pull-up resistor will set to "1" when pin is left open.

PIN DESCRIPTIONS

Name

TSSOP

Pin number

3x3mm QFN

Pin number

Type Description

VDDANA 1 11 P V

for analog Circuitry.

XIN 2 12 I Crystal input pin. (See Crystal Specifications on page 4).

XOUT 3 13 O Crystal output pin. (See Crystal Specifications on page 4).

SEL2 4 14 I Output frequency Selector pin.

OE_CTRL 5 15 I

Output enable control pin. (See OUTPUT ENABLE LOGIC

LEVELS above).

VCON 6 16 I Voltage control input.

GNDANA 7 1 P Ground for analog circuitry.

LP 8 2 -

LM 9 3 -

Tuning inductor connection. The inductor is recommended

to be a high Q small size 0402 or 0603 SMD component,

and must be placed between LP and adjacent LM pin.

Place inductor as close to the IC as possible to minimize

parasitic effects and to maintain inductor Q.

GNDBUF 10 4 P GND connection for output buffer circuitry.

Q 11 5 O LVPECL or LVDS output.

VDDBUF 12 6 P

connection for output buffer circuitry. VDDBUF should be

separately decoupled from other VDDs whenever possible.

QBAR 13 7 O

Complementary LVPECL, LVDS, Or single ended LVCMOS

output.

GNDBUF 14 8 P GND connection for output buffer circuitry.

SEL1 15 9 I Output frequency Selector pin.

SEL0 16 10 I Output frequency Selector pin.

(Preliminary)

38MHz to 320MHz Low Phase Noise VCXO

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 8/19/09 Page 3

FREQUENCY SELECTION TABLE

SEL2 SEL1 SEL0 Selected Multiplier/Output Frequency

0 0 0 VCO Max*

0 0 1 VCO Min*

0 1 0 Reserved

0 1 1 Reserved

1 0 0 F

XTAL

x 2

1 0 1 F

XTAL

x 8

1 1 0 F

XTAL

x 16

1 1 1 F

XTAL

x 4

All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0.

* Special Test Modes to help selecting the inductor value for the target output frequency.

PERFORMANCE TUNING & INDUCTOR VALUE SELECTION

Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor

values for your application. In addition, the chart below could be used as a reference for quick inductor value

selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning

Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance

enhancement of your custom board design, please follow the following instruction:

Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max”

represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output

frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are

around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency

is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock

in the middle of its tuning range with maximum margin on either side.

P1-P3 P4-P6 P7-P9 P10-P10

PL580-35OC-R

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PL580-35OC-R

PL580-35OC-R

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