NB4L858M
http://onsemi.com
6
Table 6. AC CHARACTERISTICS V
CC
= 2.3 V to 3.6 V, GND = 0 V; (Note 4)
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
)
f
in
≤ 2 GHz
(See Figure 2) f
in
≤ 3 GHz
f
in
≤ 3.5GHz
280
235
170
365
310
220
280
235
170
365
310
220
280
235
170
365
310
220
mV
f
DATA
Maximum Operating Data Rate 3 3 3 Gb/s
t
PLH
,
t
PHL
Propagation Delay to Output Differential
D/D
to Q/Q 220 350 450 220 350 450 220 350 450
ps
t
SWiITCH
SELyx to Valid Qyx Output (Note 9) 0.5 1.0 0.5 1.0 0.5 1.0 ns
t
SKEW
Within −Device Skew (Note 5)
Within −Device Skew (Note 6)
Device to Device Skew (Note 9)
12
25
100
12
25
100
12
25
100
ps
t
JITTER
RMS Random Clock Jitter (Note 8) f
in
=2 GHz
f
in
=3 GHz
Peak−to−Peak Data Dependent Jitter f
in
=2.5Gb/s
(Note 9) f
in
=3.2Gb/s
Crosstalk Induced RMS Jitter (Note 11)
0.5
1.0
2.0
10
0.5
0.5
1.0
5.0
10
0.5
0.5
1.0
2.0
10
0.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration)
100 800 100 800 100 800 mV
t
r
t
f
Output Rise/Fall Times @ 0.5 GHz Q
x
, Q
x
(20% − 80%)
80 120 80 120 80 120 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All loading with an external R
L
= 50 W to V
CC
. Input edge rates 40 ps
(20% − 80%).
5. Worst−case difference between QA0 and QA1 from either DA0 or DA1 (or between QB0 and QB1 from either DB0 or DB1 respectively),
when both outputs come from the same input.
6. Worst−case difference between QA and QB outputs, when DA or DB inputs are shorted.
7. Additive RMS jitter with 50% duty cycle input clock signal.
8. Additive peak−to−peak data dependent jitter with input NRZ data signal.
9. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
10.LVTTL/LVCMOS input edge rate less than 1.5 ns
11. Data taken on the same device under identical condition.
Figure 2. Output Voltage Amplitude (V
OUTPP
) versus Input Clock Frequency (fin) and Temperature
0
50
100
150
200
250
300
350
400
1 1.5 2 2.5 3 3.5
VOLTAGE (mV)
INPUT CLOCK FREQUENCY (GHz)
25°C
−40°C
85°C
