74VHC573FT
1
CMOS Digital Integrated Circuits Silicon Monolithic
74VHC573FT
74VHC573FT
74VHC573FT
74VHC573FT
Start of commercial production
2013-03
1.
1.
1.
1. Functional Description
Functional Description
Functional Description
Functional Description
• Octal D-Type Latch with 3-State Outputs
2.
2.
2.
2. General
General
General
General
The 74VHC573FT is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with
silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS
low power dissipation.
This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE).
When the OE input is high, the eight outputs are in a high impedance state.
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
3.
3.
3.
3. Features
Features
Features
Features
(1) AEC-Q100 (Rev. H) (Note 1)
(2) Wide operating temperature range: T
opr
= -40 to 125
(3) High speed: t
pd
= 4.5 ns (typ.) at V
CC
= 5.0 V
(4) Low power dissipation: I
CC
= 4.0 µA (max) at T
a
= 25
(5) High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
(6) Power-down protection is provided on all inputs.
(7) Balanced propagation delays: t
PLH
≈ t
PHL
(8) Wide operating voltage range: V
CC(opr)
= 2.0 V to 5.5 V
(9) Low noise: V
OLP
= 1.0 V (max)
(10) Pin and function compatible with the 74 series
(74AC/HC/AHC/LV etc.) 573 type.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
4.
4.
4.
4. Packaging
Packaging
Packaging
Packaging
2017-02-22
Rev.4.0
©2016 Toshiba Corporation
