74VHC573FT
8
12.7.
12.7.
12.7.
12.7. AC Characteristics (Unless otherwise specified, T
AC Characteristics (Unless otherwise specified, T
AC Characteristics (Unless otherwise specified, T
AC Characteristics (Unless otherwise specified, T
a
a
a
a
= 25
= 25
= 25
= 25
, Input: t
, Input: t
, Input: t
, Input: t
r
r
r
r
= t
= t
= t
= t
f
f
f
f
= 3 ns)
= 3 ns)
= 3 ns)
= 3 ns)
Characteristics
Propagation delay time
(LE-Q)
Propagation delay time
(D-Q)
3-state output enable time
3-state output disable time
Output skew
Input capacitance
Output capacitance
Power dissipation capacitance
Symbol
t
PLH
,t
PHL
t
PLH
,t
PHL
t
PZL
,t
PZH
t
PLZ
,t
PHZ
t
osLH
,t
osHL
C
IN
C
OUT
C
PD
Note
(Note 1)
(Note 2)
Test Condition
R
L
= 1 kΩ
R
L
= 1 kΩ
V
CC
(V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
C
L
(pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
50
50
Min
Typ.
7.6
10.1
5.0
6.5
7.0
9.5
4.5
6.0
7.3
9.8
5.2
6.7
10.7
6.7
4
6
29
Max
11.9
15.4
7.7
9.7
11.0
14.5
6.8
8.8
11.5
15.0
7.7
9.7
14.5
9.7
1.5
1.0
10
Unit
ns
ns
ns
ns
ns
pF
pF
pF
Note 1: Parameter guaranteed by design. (t
osLH
= |t
PLH
m-t
PLH
n|, t
osHL
= |t
PHL
m-t
PHL
n|)
Note 2: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load. Average operating current can be obtained by the equation.
I
CC(opr)
= C
PD
× V
CC
× f
IN
+ I
CC
/8 (per latch)
And the total C
PD
when n pcs. of latch operate can be gained by the following equation.
C
PD
(total) = 21 + 8 × n
12.8.
12.8.
12.8.
12.8. AC Characteristics
AC Characteristics
AC Characteristics
AC Characteristics
(Unless otherwise specified, T
(Unless otherwise specified, T
(Unless otherwise specified, T
(Unless otherwise specified, T
a
a
a
a
= -40 to 85
= -40 to 85
= -40 to 85
= -40 to 85
, Input: t
, Input: t
, Input: t
, Input: t
r
r
r
r
= t
= t
= t
= t
f
f
f
f
= 3 ns)
= 3 ns)
= 3 ns)
= 3 ns)
Characteristics
Propagation delay time
(LE-Q)
Propagation delay time
(D-Q)
3-state output enable time
3-state output disable time
Output skew
Input capacitance
Symbol
t
PLH
,t
PHL
t
PLH
,t
PHL
t
PZL
,t
PZH
t
PLZ
,t
PHZ
t
osLH
,t
osHL
C
IN
Note
(Note 1)
Test Condition
R
L
= 1 kΩ
R
L
= 1 kΩ
V
CC
(V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
C
L
(pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
50
50
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
14.0
17.5
9.0
11.0
13.0
16.5
8.0
10.0
13.5
17.0
9.0
11.0
16.5
11.0
1.5
1.0
10
Unit
ns
ns
ns
ns
ns
ns
pF
Note 1: Parameter guaranteed by design. (t
osLH
= |t
PLH
m-t
PLH
n|, t
osHL
= |t
PHL
m-t
PHL
n|)
2017-02-22
Rev.4.0
©2016 Toshiba Corporation
