MAX4717/MAX4718
Detailed Description
The MAX4717/MAX4718 high-speed, low-voltage, low on-
resistance (R
ON
), dual SPDT analog switches operate
from a single +1.8V to +5.5V supply. The switches feature
break-before-make switching operation and fast switch-
ing speeds (t
ON
= 80ns (max), t
OFF
= 40ns (max)).
These switches have low 15pF on-channel capaci-
tance, which allows for 12Mbps switching of the data
signals for USB 1.0/1.1 applications. The MAX4717 is
designed to switch D+ and D- USB signals with a guar-
anteed skew of less than 2ns (see Figure 4) as mea-
sured from 50% of the input signal to 50% of the output
signal.
Applications Information
Digital Control Inputs
The MAX4717/MAX4718 logic inputs accept up to
+5.5V regardless of supply voltage. For example, with
a +3.3V supply, IN_ can be driven low to GND and high
to +5.5V allowing for mixing of logic levels in a system.
Driving the control logic inputs rail-to-rail minimizes
power consumption. For a +3V supply voltage, the
logic thresholds are 0.5V (low) and 1.4V (high); for a
+5V supply voltage, the logic thresholds are 0.8V (low)
and 2.0V (high).
Analog Signal Levels
The on-resistance of the MAX4717/MAX4718 changes
very little for analog input signals across the entire supply
voltage range (see the Typical Operating Characteristics).
The switches are bidirectional, so the NO_, NC_, and
COM_ pins can be either inputs or outputs.
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current-limited.
UCSP Application Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board techniques, bump-pad layout, and recommend-
ed reflow temperature profile as well as the latest infor-
mation on reliability testing results, go to the Maxim
web site at www.maxim-ic.com/ucsp to find the
Application Note: USCPA Wafer-Level Chip-Scale
Package.
Chip Information
TRANSISTOR COUNT: 235
PROCESS: BiCMOS
4.5
/20
, 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
10 ______________________________________________________________________________________
PIN
UCSP
µMAX/
TDFN
NAME FUNCTION
A1 7 NC2
Analog Switch 2—Normally Closed
Terminal
A2 8 IN2
Analog Switch 2—Digital Control
Input
A3 9 COM2
Analog Switch 2—Common
Terminal
A4 10 NO2
Analog Switch 2—Normally Open
Terminal
B1 6 GND Ground. Connection.
B4 1 V+ Positive-Supply Voltage
C1 5 NC1
Analog Switch 1—Normally Closed
Terminal
C2 4 IN1
Analog Switch 1—Digital Control
Input
C3 3 COM1
Analog Switch 1—Common
Terminal
C4 2 NO1
Analog Switch 1—Normally Open
Terminal
——EP
Exposed Pad (for TDFN package
only). Connect to ground.
Pin Description
MAX4717/MAX4718
4.5
/20
, 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
______________________________________________________________________________________ 11
Test Circuits/Timing Diagrams
t
r
< 5ns
t
f
< 5ns
50%
V
IL
LOGIC
INPUT
R
L
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
N_
V
IH
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
V+
C
L
V+
V
OUT
MAX4717/
MAX4718
Figure 1. Switching Time
50%
V
IH
V
IL
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
BBM
LOGIC
INPUT
R
L
300
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V+
V+
C
L
35pF
V
N_
COM_
MAX4717/
MAX4718
Figure 2. Break-Before-Make Interval
MAX4717/MAX4718
4.5
/20
, 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
12 ______________________________________________________________________________________
IN+
IN-
IN1 IN2
C
L
C
L
OUT+
OUT-
V
IN+
V
IN-
V
OUT+
V
OUT-
NC1 OR
NO1
NC2 OR
NO2
COM1
COM2
0V
V+
0V
V+
0V
V+
0V
V+
t
SKEW
t
INFALL
t
INRISE
t
OUTFALL
t
OUTRISE
RISE TIME DELAY = |t
INRISE
- t
OUTRISE
|
FALL TIME DELAY = |t
INFALL
- t
OUTFALL
|
RISE TIME TO FALL TIME MISMATCH = |t
OUTFALL
- t
OUTRISE
|
50%
50%
50%
50%
90%
10%
90%
10%
90%
10%
90%
10%
MAX4717
R
S
R
S
V
IL
TO V
IH
Figure 3. Output Signal Skew
Test Circuits/Timing Diagrams (continued)

MAX4717EUB+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs 4.5/20Ohm 300MHz SPDT Analog Switch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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