Data Sheet AD823
Rev. E | Page 13 of 20
THEORY OF OPERATION
The AD823 is fabricated on the Analog Devices, Inc. proprietary
complementary bipolar (CB) process that enables the construction
of PNP and NPN transistors with similar f
T
’s in the 600 MHz to
800 MHz region. In addition, the process also features N-Channel
JFETs that are used in the input stage of the AD823. These
process features allow the construction of high frequency, low
distortion op amps with picoamp input currents. This design
uses a differential output input stage to maximize bandwidth
and headroom (see Figure 36). The smaller signal swings
required on the S1P/S1N outputs reduce the effect of the
nonlinear currents due to junction capacitances and improve
the distortion performance. With this design, harmonic
distortion of better than −91 dB @ 20 kHz into 600 Ω with
V
OUT
= 4 V p-p on a single 5 V supply is achieved. The
complementary common emitter design of the output stage
provides excellent load drive without the need for emitter
followers, thereby improving the output range of the device
considerably with respect to conventional op amps. The
AD823 can drive 20 mA with the outputs within 0.6 V of the
supply rails. The AD823 also offers outstanding precision for a
high speed op amp. Input offset voltages of 1 mV maximum
and offset drift of 2 µV/°C are achieved through the use of the
Analog Devices advanced thin film trimming techniques.
A nested integrator topology is used in the AD823 (see Figure 37).
The output stage can be modeled as an ideal op amp with a
single-pole response and a unity-gain frequency set by
transconductance g
m2
and Capacitor C2. R1 is the output
impedance of the input stage; g
m
is the input transconductance.
C1 and C5 provide Miller compensation for the overall op amp.
The unity-gain frequency occurs at g
m
/C5. Solving the node
equations for this circuit yields
( )
[ ]
( )
+
×++
=
111
2m
g
C2
sA2C1sR1
A0
Vi
V
OUT
where:
A0 = g
m
g
m2
R2R1 (open-loop gain of op amp).
A2 = g
m2
R2 (open-loop gain of output stage).
The first pole in the denominator is the dominant pole of the
amplifier and occurs at ~18 Hz. This equals the input stage
output impedance R1 multiplied by the Miller-multiplied value
of C1. The second pole occurs at the unity-gain bandwidth of
the output stage, which is 23 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard 2-stage architecture would allow.
V
CC
V
INP
V
INN
V
EE
R42 R37
J1
J6
I1
C6
R33
I2
R43
I3
Q56
S1P
Q72
Q61
Q46
I5
V
BE
+ 0.3V
S1N
Q53
Q35
Q48
V
CC
Q21
Q62 Q60
Q54
R44
R28
Q52
I4
Q59
A = 1
V
B
C1
Q17
A = 19
V
OUT
C2
Q18
Q49
Q55
Q43
I6
Q44
A = 1
Q57
A = 19
Q58
V1
00901-036
Figure 36. Simplified Schematic
