AD823 Data Sheet
Rev. E | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 36 V
Internal Power Dissipation
PDIP (N) 1.3 W
SOIC (R) 0.9 W
Input Voltage (Common Mode) ±V
S
Differential Input Voltage ±V
S
Output Short-Circuit Duration See Figure 4
Storage Temperature Range N, R
−65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature Range
(Soldering, 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Specification is for device in free air.
Table 5. Thermal Resistance
Package Type
θ
JA
Unit
8-Lead PDIP 90 °C/W
8-Lead SOIC
160
°C/W
MAXIMUM POWER DISSIPATION (W)
AMBIENT TEMPERATURE (°C)
2.0
1.5
0
–50 90–40 –30 –20 –10 0 10 20 30 50 60 70 8040
1.0
0.5
8-LEAD PDIP
8-LEAD SOIC
T
J
= 150°C
00901-004
Figure 4. Maximum Power Dissipation vs. Temperature
ESD CAUTION
Data Sheet AD823
Rev. E | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE (µV)
80
0
–200 200–150
UNITS
–100 –50 0 50 100 150
70
40
30
20
10
60
50
+V
S
= +5V
314 UNITS
σ = 40µV
00901-005
Figure 5. Typical Distribution of Input Offset Voltage
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
22
0
–6 7–5
UNITS
–4 –3 –2 3 4 5
20
6
4
2
18
16
14
12
10
8
6–1 0 1 2
+V
S
= +5V
–55°C TO +125°C
103 UNITS
00901-006
Figure 6. Typical Distribution of Input Offset Voltage Drift
COMMON-MODE VOLTAGE (V)
–4
INPUT BIAS CURRENT (pA)
–5
0
–1
–2
–3
3
+V
S
= +5V
1
2
–4 –3 –2 –1 0 1 5432
00901-007
Figure 7. Input Bias Current vs. Common-Mode Voltage
INPUT BIAS CURRENT (pA)
100
0
UNITS
0
90
40
30
20
10
80
70
+V
S
= +5V
317 UNITS
σ = 0.4pA
50
60
1 2
3 4 5 6 7 8 9 10
00901-008
Figure 8. Typical Distribution of Input Bias Current
TEMPERATURE (°C)
0.1
INPUT BIAS CURRENT (pA)
0
100
10
1
10000
+V
S
= +5V
V
CM
= 0V
1000
25 50 75 100 125
00901-009
Figure 9. Input Bias Current vs. Temperature
COMMON-MODE VOLTAGE (V)
0.1
INPUT BIAS CURRENT (pA)
–16
100
10
1
1000
–12 4 8 12 16
V
S
= ±15V
–8 –4 0
00901-010
Figure 10. Input Bias Current vs. Common-Mode Voltage
AD823 Data Sheet
Rev. E | Page 8 of 20
LOAD RESISTANCE ()
60
80
70
90
100
110
OPEN-LOOP GAIN (dB)
100
1k
10k
100k 500k
V
S
= ±2.5V
00901-011
Figure 11. Open-Loop Gain vs. Load Resistance
OUTPUT VOLTAGE (V)
0.1
OPEN-LOOP GAIN (k
–2.5
100
10
1
1000
–2.0 –0.5 0.5 1.0 2.5
R
L
= 10k
–1.5 –1.0 0 1.5 2.0
R
L
= 1kΩ
R
L
= 100Ω
V
V
)
00901-012
Figure 12. Open-Loop Gain vs. Output Voltage, V
S
= ±2.5 V
FREQUENCY (Hz)
–40
–110
–50
–80
–90
–100
–60
–70
100 100k
THD (dB)
1k 10k
+V
S
= +3V
V
OUT
= 2V p-p
R
L
= 100
+V
S
= +3V
V
OUT
= 2V p-p
R
L
= 5k
+V
S
= +5V
V
OUT
= 2V p-p
R
L
= 5k
V
S
= ±15V
V
OUT
= 10V p-p
R
L
= 600
V
S
= ±2.5V
V
OUT
= 2V p-p
R
L
= 1k
1M
ALL
OTHERS
00901-013
Figure 13. Total Harmonic Distortion vs. Frequency
TEMPERATURE (°C)
86
90
89
88
87
95
91
92
93
94
OPEN-LOOP GAIN (dB)
–55
+V
S
= +5V
R
L
= 2k
–25 5 35 65 95 125
00901-014
Figure 14. Open-Loop Gain vs. Temperature
FREQUENCY (Hz)
100
–20
80
40
20
0
60
100 100M1k 10k 100k 1M 10M
OPEN-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
PHASE
GAIN
R
L
= 2k
C
L
= 20pF
100
–20
80
40
20
0
60
00901-015
Figure 15. Open-Loop Gain and Phase Margin vs. Frequency
FREQUENCY (Hz)
100
30
3
10 1M100 1k 10k 100k
10
+V
S
= +5V
INPUT VOLTAGE NOISE (nV/√Hz)
00901-016
Figure 16. Input Voltage Noise vs. Frequency

AD823ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers 17MHz RR FET Input Dual
Lifecycle:
New from this manufacturer.
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