LTC4352
11
4352fa
SOURCE
LTC4352
TO LOAD
5V
Q1
Si7336ADP
4352 F07
V
IN
GATE OUT
C2
0.1µF
R7
1k
GND
12V
CPO
Figure 7. 5V Ideal Diode with External 12V Powering CPO for
Faster Start-up and Refresh
applicaTions inForMaTion
External CPO Supply
The internal charge pump takes milliseconds to charge
up the CPO pin capacitor especially during device power
up. This time can be shortened by connecting an external
supply to the CPO pin. A series resistor is needed to limit
the current into the internal clamp between the CPO and
SOURCE pins. The CPO supply should also be higher than
the main input supply to meet the gate drive requirements
of the MOSFET. Figure 7 shows such a 5V ideal diode ap-
plication, where a 12V supply is connected to the CPO pin
through a 1k resistor. The 1k limits the current into the
CPO pin to 5.3mA, when the SOURCE pin is grounded.
Input Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current can cause transients that
exceed the 24V Absolute Maximum Rating of the V
IN
and
OUT pins. In ORing applications using a single MOSFET, one
surge suppressor connected from OUT to ground clamps
all the inputs. In the absence of a surge suppressor, an
output capacitance of 10μF is sufficient in most applications
to prevent the transient from exceeding 24V. Back-to-back
MOSFET applications, depending on voltage levels, may
require a surge suppressor on each supply input.
Design Example
The following design example demonstrates the calcula-
tions involved for selecting components in a 12V system
with 10A maximum load current (see Figure 1).
First, calculate the R
DS(ON)
of the MOSFET to achieve the
desired forward drop at full load. Assuming a V
FWD
of
50mV (which is comfortably below the 200mV minimum
open MOSFET fault threshold):
R
DS ON
( )
≤
V
FWD
I
LOAD
=
50mV
10A
= 5mΩ
The Si7336ADP offers a good solution, in a SO-8 sized
package, with a maximum R
DS(ON)
of 4mΩ and BV
DSS
of
30V. The maximum power dissipation in the MOSFET is:
P = I
2
LOAD
• R
DS(ON)
= (10A)
2
• 4mΩ = 0.4W
With a maximum steady-state thermal resistance, θ
JA
,
of 65°C/W, 0.4W causes a modest 26°C rise in junction
temperature of the Si7336ADP above the ambient.
The input capacitance, C
ISS
, of the Si7336ADP is about
6500pF. Slightly exceeding the 10x recommendation, a
0.1µF capacitor is selected for C2.
